Digital Step Attenuator
Simplified Schematic
DAT-31R5-PP+
RF Input
RF Out
16dB
8dB
4dB
2dB
0.5dB
1dB
Parallel Control
Latch Enable
Internal Control Logic Interface
The DAT-31R5-PP+ parallel interface consists of 6 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
C16
C8
C4
C2
C1
C0.5
State
Reference
0.5 (dB)
1 (dB)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
2 (dB)
4 (dB)
8 (dB)
16 (dB)
31.5 (dB)
Note: Not all 64 possible combinations of C0.5 - C16 are shown in table
The parallel interface timing requirements are defined by Figure 1 (Parallel Interface Timing Diagram) and
Table 2 (Parallel Interface AC Characteristics), and switching speed.
For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW (per Figure 1) to latch new attenuation state into device.
For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation
state control values will change device state to new attenuation. Direct mode is ideal for manual control of
the device (using hardwire, switches, or jumpers).
Figure 1: Parallel Interface Timing Diagram
Table 2. Parallel Interface AC Characteristics
Symbol
Parameter
Min.
10
Max.
Units
ns
LE
LE minimum pulse width
tLEPW
tPDSUP
tPDHLD
Data set-up time before
clock rising edge of LE
10
ns
Parallel Data
C16:C0.5
Data hold time
after clock falling edge of LE
10
ns
tLEPW
tPDSUP
tPDHLD
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MINI [ MINI-CIRCUITS ]
