35.0-45.0 GHz GaAs MMIC
Power Amplifier
October 2005 - Rev 21-Oct-05
App Note [1] Biasing
-
It is recommended to separately bias each amplifier stage Vd1 through Vd4 at Vd(1,2,3,4)=5.0V with Id1=35mA, Id2=60mA,
P1018
Id3=125mA and Id4=245mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will
alter the effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a
total drain current Id(total)=465 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature
vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may
be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The
gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.7V.
Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative
gate bias is available before applying the positive drain supply.
App Note [2] Bias Arrangement
-
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3,4 and Vg1,2,3,4) needs to have DC bypass capacitance
(~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
App Note [3] Output Power Adjust Using Gate Control -
This device has a very useful additional feature. The output power can be adjusted by
lowering the individual or combined gate voltages towards pinch off without sacrificing much in the way of Input/Output 3rd Order Intercept Point.
Improvements to the IIP3/OIP3 data shown here while attenuating the gain are also possible with individual gate control. Data here has been taken
using combined gate control (all gates changed together) to lower the device's output power. The results are shown below. Additionally, the
accompanying graphs show the level and linearity of the typical attenuation achievable as the gate is adjusted at various levels until pinch-off.
P in=+5 dBm, linear decreas e from 5V/500 mA to 0V /0 mA (V gs=-1.6 V )
30
25
20
15
Ou tput P ower (dB m)
10
5
0
37
-5
-10
-15
-20
-25
-30
Fr e que ncy (G Hz )
37.5
38
38.5
39
39. 5
40
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 4 of 6
Characteristic Data and Specifications are subject to change without notice.
©2005
Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
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