CMM0530-LC
Electrical Characteristics
Advanced Product Information - May 1999
(2 of 4)
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.5 V, in Celeritek test fixture.
Digital Bias
Parameter
Condition
Min
Typ
Max
Analog Bias
Min
Typ
Max
Units
Frequency Range
Pout - TDMA Operation
Pout - CDMA Operation
Pout - Analog Operation
Efficiency
824
+30.0
+28.5
928
824
928
Meets IS-136 TDMA mask
Meets IS-98 CDMA mask
AMPS (under dual mode operation)
IS-136 TDMA @ +30 dBm
IS-95 CDMA @ +28 dBm
AMPS @ +31.5 dBm
(under dual mode operation)
Harmonics
2nd @ Pout = +31.5 dBm
3rd @ Pout = +31.5 dBm
Adjacent Channel Power
Pout = +30 dBm TDMA ±30 KHz
Alternate Channel Power
Pout = +30 dBm TDMA ±60 KHz
Adjacent Channel Power
Pout = +28 dBm CDMA ±898 KHz
Alternate Channel Power
Pout = +28 dBm CDMA ±1980 KHz
Noise Power in Receive Band 30 kHz BW
Gain
@ Pout = +28.5 dBm, +30 dBm
@ Pout = +31.5 dBm
Gain Ripple
824-849 or 880-910 MHz
Gain Variation
Over supply voltage
Gain Variation
Over temperature
Power Output Control Range Vdd = 0 to 3.5 V
Quiescent Current
No RF, TDMA mode
No RF, CDMA mode
Noise Figure
VSWR
Input (In Celeritek test fixture)
Stability
8:1 VSWR in band
10:1 VSWR out of band
– Continued from Page 1 –
+31.5
42
37
55
57
-30
-35
MHz
dBm
dBm
dBm
%
%
%
dBc
dBc
dBc
dBc
dBc/30 KHz
dBc/30 KHz
dBm
dB
dB
dB
dB/V
dB/°C
dB
mA
mA
dB
dBc/30 KHz
dBc/30 KHz
-26
-45
-45
-55
26
-94
29
24
1.5
2
0.03
50
200
170
3.5
2.0:1
-80
-80
2
0.03
27
1.5
3.5
2.0:1
-80
-80
in-line inductance are shown in the evaluation board on page 4.
Matching Circuits
Output matching and input matching cir-
cuits are required to achieve the RF specifications in this data
sheet. The recommend matching circuits are identical to the
matching circuits for the evaluation board shown on Page 4.
For output power matching, shunt capacitors along the trans-
mission line connected to Pins 6 and 7 as well as the bond
wire inside the package from the output leads to the output
FET are used to transform 50Ω impedance to the load line
resistance of the output FET. The placements and the values
of the capacitor are important in achieving the performance
desired. Matching circuits for frequencies other than the one
shown can be achieved by changing the capacitor value and
the placement position of the capacitor. The device can be
designed to work from UHF to around 3 GHz.
Supply Ramping
To obtain power ramping, gate supply con-
trol is recommended. Drain supply voltage can also be used.
Modulation
When biased as specified, the CMM0530-LC will
achieve the required adjacent channel response for the digital
system specified. Celeritek tests each product under digital
modulation to ensure correlation to customer applications.
Thermal
1. The copper pad on the backside of the CMM0530-LC must
be soldered to the ground plane.
2. All 8 leads of the package must be soldered to the appropri-
ate electrical connection.
Typical Performance
Gain & IS-136 TDMA Output Power
vs Frequency Over Voltage @ +25°C
Power Out, dBm
31.5
3.3 V
3.0 V
29.5
2.7 V
3.3 V
3.0 V
2.7 V
27.5
824
Frequency, MHz
849
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
Gain, dB
29.5
MIMIX [ MIMIX BROADBAND ]
