43.5-46.5 GHz GaAs MMIC
Power Amplifier
April 2005 - Rev 01-Apr-05
App Note [1] Biasing
-
It is recommended to separately bias each amplifier stage Vd1 through Vd3 at Vd(1,2,3)=5.0V with Id1=Id2=360mA, and
44MPA0478
App Note [2] Bias Arrangement
-
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3 and Vg1,2,3) needs to have DC bypass capacitance
(~100-200 pf ) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended. All DC pads have been tied
together on chip and can be biased from either side.
MTTF Tables (TBD)
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
165.2 deg Celsius
191.4 deg Celsius
217.1 deg Celsius
Rth
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
MTTF Hours
uc
VD3A
R=16 Ohm
3
1
2
2
1
3
FITs
od
78.5º C/W
82.8º C/W
87.0º C/W
VD2A
R=15 Ohm
R=15 Ohm
R=15 Ohm
R=15 Ohm
3.65E+06
3.89E+05
5.48E+04
2.74E+02
2.57E+03
9.13E+03
Device Schematic
e-
pr
VG1A
VD1A
VG2A
R=20 Ohm
R=16 Ohm
1
2
1
3
Bias Conditions:
Vd=5V, Id1=Id2=360 mA, Id3=720 mA
VG3A
R=20 Ohm
R=20 Ohm
2
RFIN
3
Pr
4
3
R=16 Ohm
R=16 Ohm
3
4
1
2
2
1
R=16 Ohm
R=16 Ohm
3
1
2
1
2
1
3
1
3
2
2
R=50 Ohm
3
R=20 Ohm
R=20 Ohm
R=16 Ohm
R=20 Ohm
R=16 Ohm
VG1B
VD1B
VG2B
VD2B
VG3B
VD3B
tio
R=50 Ohm
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pf ) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads. All DC pads have been tied together on chip and can be biased from either side.
RF OUT
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 4 of 5
Characteristic Data and Specifications are subject to change without notice.
©2005
Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
their obligation to be compliant with U.S. Export Laws.
n
Id3=720mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will alter the
effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a total drain
current Id(total)=1440 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this
gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a
single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of
the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.5V. Typically the
gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is
available before applying the positive drain supply.
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