AUSTIN SEMICONDUCTOR, INC.
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
TRANSFER OPERATIONS
TRANSFER operations are initiated when
/
T
/
R/(/O
/
E) is
LOW then
/
R
/
A
/
S goes LOW. The state of (?M
/
E)/?W
/
E when
/
R
/
A
/
S goes LOW indicates the direction of the TRANSFER
(to or from the DRAM), and DSF is used to select between
NORMAL TRANSFER, SPLIT READ TRANSFER, and AL-
TERNATE WRITE TRANSFER cycles. Each of the TRANS-
FER cycles available is described below.
READ TRANSFER (DRAM-TO-SAM TRANSFER)
If (?M
/
E)/?W
/
E is HIGH and DSF is LOW when
/
R
/
A
/
S goes
LOW, a READ TRANSFER cycle is selected. The row ad-
dress bits indicate the four 512-bit DRAM row planes that
are to be transferred to the four SAM data register planes.
The column address bits indicate the start address (or Tap
address) of the serial output cycle from the SAM data
registers.
/
C
?
A
/
S must fall for every TRANSFER in order to
load a valid Tap address. A read transfer may be accom-
plished in two ways. If the transfer is to be synchronized
with SC (REAL-TIME READ TRANSFER),
/
T
/
R/(?O
/
E) is
taken HIGH after
?/
C
/
A
/
S goes LOW. If the transfer does not
have to be synchronized with SC (READ TRANSFER),
/
T
/
R/
(?O
/
E) may go HIGH before
?
C
/
A
/
S goes LOW (refer to the AC
Timing Diagrams). The 2,048 bits of DRAM data are written
into the SAM data registers and the serial shift start
address is stored in an internal 9-bit register. QSF will be
LOW if access is from the lower half (addresses 0 through
255), and HIGH if access is from the upper half (256 through
511). If
/
S
/
E is LOW, the first bits of the new row data will
appear at the serial outputs with the first SC clock pulse.
/
S
/
E enables the serial outputs and may be either HIGH or
LOW during this operation. The SAM address pointer will
increment with the SC LOW-to-HIGH transition, regard-
less of the state of
/
S
/
E. Performing a READ TRANSFER cycle
sets the direction of the SAM I/O buffers to the output
mode.
,, ,,,,,, ,
,,, ,, ,, , , ,
,
,,, ,,,,,,, ,
,,, ,, ,, , , ,
,, ,, , ,, ,,,, ,, ,,
,, ,, , , , , , ,
,
,, ,,,,,,,,,,,,,,,,,,,,
,
, , , ,,
,
,
,,,,
RAS
CAS
A0-A8
ROW 0
A0-A8 = 0
ROW 0
A0-A7 = TAP
A8 = X
ROW 1
A0-A7 = TAP
A8 = X
ME/WE
TR/OE
DSF
SC
SDQ
Output
QSF
,,,,
ROW 0
0
1
7
8
9
255
260
319
320
321
ROW 0
ROW 0
ROW 0
(NORMAL) READ TRANSFER
FROM: ROW 0
TO:
FULL SAM,
SAM I/O IS SET TO OUTPUT
MODE AND SERIAL OUTPUT
FROM LOWER SAM BEGINS
(QSF GOES LOW)
SPLIT READ TRANSFER
(OPTIONAL)
FROM: ROW 0
TO:
UPPER SAM,
TAP ADDRESS = 4
SERIAL OUTPUT FROM
LOWER SAM CONTINUES
SPLIT READ TRANSFER
SERIAL OUTPUT
SWITCHES FROM
LOWER SAM TO
UPPER SAM (QSF
GOES HIGH)
FROM: ROW 1
TO:
LOWER SAM,
TAP ADDRESS = 0 TO 255
SERIAL OUTPUT FROM
UPPER SAM CONTINUES
(QSF REMAINS HIGH)
Figure 4
TYPICAL SPLIT-READ-TRANSFER INITIATION SEQUENCE
MT42C4256 883C
REV. 3/97
DS000016
,
,
,
,
DON’T CARE
UNDEFINED
3-35
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MICROSS [ MICROSS COMPONENTS ]
