AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
NONPERSISTENT MASKED BLOCK WRITE
The MASKED WRITE functions can also be used during
BLOCK WRITE cycles. NONPERSISTENT MASKED
BLOCK WRITE operates exactly like the normal NONPER-
SISTENT MASKED WRITE, except that the mask is now
applied to four column locations instead of just one.
Like NONPERSISTENT MASKED WRITE, the combina-
tion of
?
M
/
E/(?W
/
E) LOW and DSF LOW when
/
R
/
A
/
S goes LOW
initiates a NONPERSISTENT MASKED cycle. The DSF pin
must be driven HIGH when
/
C
/
A
/
S goes LOW, to perform the
NONPERSISTENT MASKED BLOCK WRITE. By using
both the column mask input and the MASKED WRITE
function, any combination of the four bit planes or column
locations may be masked.
PERSISTENT MASKED BLOCK WRITE
This cycle is also performed exactly like the normal
PERSISTENT MASKED WRITE except that DSF is HIGH
when
/
C
/
A
/
S goes LOW to indicate the BLOCK WRITE func-
tion. Both the mask data register and the color register must
be loaded with the appropriate data prior to starting a
PERSISTENT MASKED BLOCK WRITE.
LOAD MASK DATA REGISTER
The LOAD MASK REGISTER operation and timing are
identical to a normal WRITE cycle except that DSF is HIGH
when
/
R
/
A
/
S goes LOW. As shown in the Truth Table, the
combination of
/
T
/
R/(/O
/
E),
?
M
/
E/(?W
/
E), and DSF being HIGH
when
/
R
/
A
/
S goes LOW indicates the cycle is a LOAD REGIS-
TER cycle. DSF is used when
/
C
/
A
/
S goes LOW to select the
register to be loaded and must be LOW for a LOAD MASK
REGISTER cycle. The data present on the DQ lines will then
be written to the mask data register.
Note:
For a normal DRAM WRITE cycle, the mask data
register is disabled but not modified. The contents of
mask data register will not be changed unless a NON-
PERSISTENT MASKED WRITE cycle or a LOAD
MASK REGISTER cycle is performed.
The row address supplied will be refreshed, but it is not
necessary to provide any particular row address. The col-
umn address inputs are ignored during a LOAD MASK
REGISTER cycle.
The mask data register contents are used during PERSIS-
TENT MASKED WRITE and PERSISTENT MASKED
BLOCK WRITE cycles to selectively enable writes to the
four DQ planes.
LOAD COLOR REGISTER
A LOAD COLOR REGISTER cycle is identical to the
LOAD MASK REGISTER cycle except DSF is HIGH when
/
C
/
A
/
S goes LOW. The contents of the color register are
retained until changed by another LOAD COLOR REGIS-
TER cycle (or the part loses power) and are used as data
inputs during BLOCK WRITE cycles.
AS42C4256 883C
REV. 3/97
DS000016
3-34
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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