AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
PIN DESCRIPTIONS
PIN
NUMBERS
1
4
SYMBOL
SC
/
T
/
R//O
/
E
TYPE
Input
Input
DESCRIPTION
Serial Clock: Clock input to the serial address counter for the SAM
registers.
Transfer Enable: Enables an internal TRANSFER operation at
/
R
/
A
/
S
(H
>
L), or
Output Enable: Enables the DRAM output buffers when taken LOW
after
/
R
/
A
/
S goes LOW (/C
/
A
/
S must also be LOW), otherwise the
output buffers are in a High-Z state.
7
?
M
/
E/?W
/
E
Input
Mask Enable: If
?
M
/
E/?W
/
E is LOW at the falling edge of
/
R
/
A
/
S a
MASKED WRITE cycle is performed, or
Write Enable:
?
M
/
E/?W
/
E is also used to select a READ (?
?
M
/
E/?W
/
E = H)
or WRITE (?
?
M
/
E/?W
/
E = L) cycle when accessing the DRAM. This
includes a READ TRANSFER (?
?
M
/
E/?W
/
E = H) or
WRITE TRANSFER (?
?
M
/
E/?W
/
E = L).
25
/
S
/
E
Input
Serial Port Enable:
/
S
/
E enables the serial I/O buffers and allows a
serial READ or WRITE operation to occur, otherwise the output
buffers are in a High-Z state.
/
S
/
E is also used during a WRITE
TRANSFER operation to indicate whether a WRITE TRANSFER or
a SERIAL INPUT MODE ENABLE cycle is performed.
Special Function Select: DSF is used to indicate which special
functions (BLOCK WRITE, MASKED WRITE vs. PERSISTENT
MASKED WRITE, etc.) are used on a particular access cycle.
Row Address Strobe:
/
R
/
A
/
S is used to clock-in the 9 row-address bits
and strobe the
?
M
/
E/?W
/
E,
/
T
/
R//O
/
E, DSF,
/
S
/
E,
/
C
/
A
/
S and DQ inputs. It
also acts as the master chip enable and must fall for initiation of any
DRAM or TRANSFER cycle.
Column Address Strobe:
/
C
/
A
/
S is used to clock-in the 9 column-
address bits, enable the DRAM output buffers (along with
/
T
/
R/?O
/
E),
and strobe the DSF input.
Address Inputs: For the DRAM operation, these inputs are multi-
plexed and clocked by
/
R
/
A
/
S and
/
C
/
A
/
S to select one 4-bit word out of
the 256K available. During TRANSFER operations, A0 to A8
indicate the DRAM row being accessed (when
/
R
/
A
/
S goes LOW) and
the SAM start address (when
/
C
/
A
/
S goes LOW).
DRAM Data I/O: Data input/output for DRAM cycles; inputs for
Mask Data Register and Color Register load cycles, and DQ and
Column Mask inputs for BLOCK WRITE.
Serial Data I/O: Input, output, or High-Z.
Split SAM Status: QSF indicates which half of the SAM is being
accessed. LOW if address is 0-255, HIGH if address is 256-511.
No Connect: This pin should be left either unconnected or tied to
ground.
Power Supply: +5V
±10%
Ground
22
DSF
Input
9
/
R
/
A
/
S
Input
21
/
C
/
A
/
S
Input
19, 18, 17,
A0-A8
Input
5, 6, 23, 24
DQ1-DQ4
Input/
Output
Input/
Output
Output
–
Supply
Supply
2, 3, 26, 27
20
8
14
28
AS42C4256 883C
REV. 3/97
DS000016
SDQ1-SDQ4
QSF
NC
V
CC
V
SS
3-29
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MICROSS [ MICROSS COMPONENTS ]
