UVEPROM
SMJ27C256
AS27C256
Austin Semiconductor, Inc.
SNAP! PULSE PROGRAMMING
READ/OUTPUT DISABLE
The SMJ27C256 EPROM is programmed by using the SNAP!
Pulse programming algorithm as illustrated by the flowchart
in Figure 1. This algorithm programs the device in a nominal
time of 4 seconds. Actual programming time varies as a
function of the programmer used.
When the outputs of two or more SMJ27C256s are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from the
competing outputs of the other devices. To read the output of
the selected SMJ27C256, a low-level signal is applied to E\
and G\. All other devices in the circuit should have their
outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses
of 100 microseconds (µs) followed by a byte-verification step
to determine when the addressed byte has been successfully
programmed. Up to ten 100µs pulses per byte are provided
before a failure is recognized.
LATCHUPIMMUNITY
Latchup immunity on the SMJ27C256 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to industry
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance
or packing density.
The programming mode is achieved when VPP = 13V,
VCC= 6.5V, G\ = VIH, and E\ = VIL. More than one device can
be programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is completed, all bits are verified
POWER DOWN
Active ICC supply current can be reduced from 25mA
(SMJ27C256-15 through SMJ27C256-25) to 500µA (TTL-
level inputs) or 300µA (CMOS-level inputs) by applying a high
TTL/CMOS signal to the E\ pin. In this mode all outputs are
in the high-impedance state.
with VCC = VPP = 5V.
PROGRAM INHIBIT
Programming can be inhibited by maintaining a high-level
input on E\.
ERASURE
Before programming, the SMJ27C256 is erased by exposing
the chip through the transparent lid to a high-intensity ultra-
violet light (wavelength 2537 Å). EPROM erasure before
programming is necessary to ensure that all bits are in the
logic-high state. Logic-lows are programmed into the desired
locations. A programmed logic-low can be erased only by
ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15W•s/cm2. A typical
12mW/cm2, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using the
SMJ27C256, the window should be covered with an opaque
label.
PROGRAM VERIFY
Programmed bits can be verified with VPP = 13V when
G\ = VIL, and E\ = VIH.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 is forced to 12V ±0.5V. Two identifier
bytes are accessed by A0 (terminal 10); i.e., A0=VIL accesses
the manufacturer code, which is output on DQ0-DQ7; A0=VIH
accesses the device code, which is also output on DQ0-DQ7.
All other addresses must be held at VIL. Each byte contains
odd parity on bit DQ7. The manufacturer code for these
devices is 97h and the device code is 04h.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SMJ27C256/AS27C256
Rev. 2.5 10/03
4
MICROSS [ MICROSS COMPONENTS ]
