SRAM
AS5C512K8
LOW VCC DATA RETENTION WAVEFORM
DATAꢀRETENTIONꢀMODE
VCC
4.5V
4.5V
VDR>2V
tR
tCDR
VIH-
CE\
VDR
VIL-
READ CYCLE NO. 18, 9
(Address Controlled, CE\ = OE\ = VIL, WE\ = VIH)
tRC
ADDRESS
VALID
tAA
tOH
I/O,ꢀDATAꢀINꢀ
&ꢀOUT
PreviousꢀDataꢀValid
DataꢀValid
READꢀCYCLEꢀNO.ꢀ2ꢀ2
(WE\ꢀ=ꢀVIH)
tRC
ADDRESS
CE\
tAOE
tHZOE
tLZOE
tLZCE
tACE
tHZCE
I/O,ꢀDATAꢀINꢀ
&ꢀOUT
High-Z
DataꢀValid
tPU
tPD
Icc
Don’t Care
Undefined
Micross Components reserves the right to change products or specifications without notice.
AS5C512K8
Rev. 7.5 01/13
6