AS5C512K8
GENERAL DESCRIPTION
The AS5C512K8 is a high speed SRAM. It offers flexibility in
high-speed memory applications, with chip enable (CE\) and output
enable (OE\) capabilities. These features can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
SRAM
Austin Semiconductor, Inc.
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +5V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5C512K8DJ offers the convenience and reliability of the
AS5C512K8 SRAM and has the cost advantage of a durable plastic.
The AS5C512K8DJ is footprint compatible with 36 pin CSOJ pack-
age of the SMD 5692-95600.
TSOPII with copper lead frame offers
superior thermal performance.
AS5C512K8
SRAM
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
INPUT BUFFER
ROW DECODER
1024 ROWS X
4096 COLUMNS
A0-A18
I/O
CONTROLS
4,194,304-BIT
MEMORY ARRAY
DQ8
DQ1
CE\
OE\
WE\
*POWER
DOWN
COLUMN DECODER
*On the low voltage Data Retention option.
PIN FUNCTIONS
A0 - A18
Address Inputs
Write Enable
Chip Enable
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
X = Don’t Care
TRUTH TABLE
WE\
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CE\
OE\
I/O
0
- I/O
7
V
CC
V
SS
NC
AS5C512K8
Rev. 7.5 01/13
Micross Components reserves the right to change products or specifications without notice.
2
MICROSS [ MICROSS COMPONENTS ]
