SRAM
AS5C512K8
GENERAL DESCRIPTION
standbyꢀmode,ꢀallowingꢀsystemꢀdesignersꢀtoꢀmeetꢀlowꢀstandbyꢀpowerꢀ
requirements.ꢀꢀThisꢀdeviceꢀoperatesꢀfromꢀaꢀsingleꢀ+5Vꢀpowerꢀsupplyꢀ
andꢀallꢀinputsꢀandꢀoutputsꢀareꢀfullyꢀTTL-compatible.
ꢀꢀ
TheꢀAS5C512K8ꢀisꢀaꢀhighꢀspeedꢀSRAM.ꢀꢀItꢀoffersꢀflexibilityꢀinꢀ
high-speedꢀmemoryꢀapplications,ꢀwithꢀchipꢀenableꢀ(CE\)ꢀandꢀoutputꢀ
enableꢀ(OE\)ꢀcapabilities.ꢀꢀTheseꢀfeaturesꢀcanꢀplaceꢀtheꢀoutputsꢀinꢀ
High-Zꢀforꢀadditionalꢀflexibilityꢀinꢀsystemꢀdesign.
ꢀ
TheꢀAS5C512K8DJꢀoffersꢀtheꢀconvenienceꢀandꢀreliabilityꢀofꢀtheꢀ
AS5C512K8ꢀSRAMꢀandꢀhasꢀtheꢀcostꢀadvantageꢀofꢀaꢀdurableꢀplastic.ꢀ
TheꢀAS5C512K8DJꢀisꢀfootprintꢀcompatibleꢀwithꢀ36ꢀpinꢀꢀCSOJꢀpack-
ageꢀofꢀtheꢀꢀSMDꢀ5692-95600.ꢀTSOPIIꢀwithꢀcopperꢀleadꢀframeꢀoffersꢀ
superiorꢀthermalꢀperformance.ꢀꢀꢀ
ꢀ
Writingꢀtoꢀtheseꢀdevicesꢀisꢀaccomplishedꢀwhenꢀwriteꢀenableꢀ(WE\)ꢀ
andꢀCE\ꢀinputsꢀareꢀbothꢀLOW.ꢀReadingꢀisꢀaccomplishedꢀwhenꢀWE\ꢀ
remainsꢀHIGHꢀandꢀCE\ꢀandꢀOE\ꢀgoꢀLOW.
ꢀ
Asꢀaꢀoption,ꢀtheꢀdeviceꢀcanꢀbeꢀsuppliedꢀofferingꢀꢀaꢀreducedꢀpowerꢀ
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
DQ8
DQ1
4,194,304-BIT
MEMORY ARRAY
1024 ROWS X
4096 COLUMNS
A0-A18
CE\
OE\
COLUMN DECODER
WE\
*POWER
DOWN
*On the low voltage Data Retention option.
PIN FUNCTIONS
A0 - A18
WE\
Address Inputs
Write Enable
TRUTH TABLE
MODE
STANDBY
READ
NOT SELECTED
WRITE
OE\ CE\ WE\
I/O
HIGH-Z STANDBY
ACTIVE
HIGH-Z ACTIVE
ACTIVE
POWER
CE\
Chip Enable
X
L
H
L
L
L
X
H
H
L
OE\
Output Enable
Q
H
X
I/O0 - I/O7 Data Inputs/Outputs
D
VCC
VSS
NC
Power
X = Don’t Care
Ground
No Connection
Micross Components reserves the right to change products or specifications without notice.
AS5C512K8
Rev. 7.5 01/13
2
MICROSS [ MICROSS COMPONENTS ]
