SRAM
AS5C4009LL
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1
(WE Controlled)
tWC
ADDRESS
tCW(4)
tWR(6)
CE\
tAW
tWP(3)
WE\
tAS(5)
tDH
tDW
Data Valid
DATA IN
tWHZ
tOW
DATA OUT
Data Undefined
WRITE CYCLE NO. 2
(Write Enabled Controlled)
tWC
ADDRESS
CE\
tAS(5)
tCW(4)
tWR(6)
tAW
tWP(3)
WE\
tDH
tDW
Data Valid
DATA IN
High-Z
High-Z
DATA OUT
NOTES:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature adn voltage condition, tHZ (MAX) is less than tLZ (MIN) both for a given device and from device to
device interconnection.
3. A write occurs during the overlap of a low CE\ adn a low WE\. A write begins at the latest transistion among CE\ going Low and
WE\ going Low: A write end at the earliest transistion among CE\ going High and WE\ going High, tWP is measured from the
beginning of write to the end of write.
4. tCW is measured from the CE\ going Low to end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measure from the end of write to the address change. tWR applied in case a write ends are CE\ or WE\ going High.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
7
MICROSS [ MICROSS COMPONENTS ]
