PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
NOTE 7, 12, 14
NOTES:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
All Voltages referenced to VSS (GND)
-2.0V for Pulse
≤ 20ns
ICC is dependent on output loading, specification testing per Output Load fiqures 1&2
This parameter is guaranteed but not tested
Test conditions as specified in Output Load figure 1
tCLZ, tCHZ, tOLZ, tOHZ, tWLZ and tWHZ are specified with use of Output Load fiqure 2
At any given voltage and/or temperature condition, tCHZ is less than tCLZ and tWHZ is
less than tWLZ
WE\ is High for READ Cycles
Device is continuously selected. Chip Select and Output Enable are driven to their
Active state
Address Valid prior to, or coincident with latest occuring Chip Select
Full device operation requires linear VCC ramp from VDR to VCC(MIN)
≥
50
µ
s or statble
at VCC(MIN)
≥
50
µ
s Max
Chips Select and Write Enable can initiate and terminate a WRITE Cycle
Output Enable is Inactive when HIGH
Output Enable is Active when LOW
tPOWER gives the minimum amount of time that the power supply should be at typical
VCC values unitl the first memory access can be performed
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
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