欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-9561329H9C 参数 Datasheet PDF下载

5962-9561329H9C图片预览
型号: 5962-9561329H9C
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 512KX8, 12ns, CMOS, CDFP32, CERAMIC, DFP-32]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 135 K
品牌: MICROSS [ MICROSS COMPONENTS ]
 浏览型号5962-9561329H9C的Datasheet PDF文件第1页浏览型号5962-9561329H9C的Datasheet PDF文件第2页浏览型号5962-9561329H9C的Datasheet PDF文件第3页浏览型号5962-9561329H9C的Datasheet PDF文件第4页浏览型号5962-9561329H9C的Datasheet PDF文件第6页浏览型号5962-9561329H9C的Datasheet PDF文件第7页浏览型号5962-9561329H9C的Datasheet PDF文件第8页浏览型号5962-9561329H9C的Datasheet PDF文件第9页  
SRAM  
AS5C4008  
AC TEST CONDITIONS  
Input pulse levels ................................................ Vss to 3.0V  
Input rise and fall times ................................................... 3ns  
Input timing reference levels ......................................... 1.5V  
Output reference levels .................................................. 1.5V  
Output load ............................................ See Figures 1 and 2  
Fig. 1 Output Load Equivalent  
Fig. 2 Output Load Equivalent  
9. Device is continuously selected. Chip enables and  
output enables are held in their active state.  
10. Address valid prior to, or coincident with, latest  
occurring chip enable.  
11. RC = Read Cycle Time.  
12. Chip enable and write enable can initiate and  
terminate a WRITE cycle.  
13. Output enable (OE\) is inactive (HIGH).  
14. Output enable (OE\) is active (LOW).  
15. ASI does not warrant functionality nor reliability of any  
product in which the junction temperature exceeds  
150°C. Care should be taken to limit power to accept-  
NOTES  
1. All voltages referenced to VSS (GND).  
2. -2V for pulse width < 20ns  
3. ICC is dependent on output loading and cycle rates.  
4. This parameter is guaranteed but not tested.  
5. Test conditions as specied with the output loading  
as shown in Fig. 1 unless otherwise noted.  
6. tLZCE, LZWE, LZOE, HZCE, HZOE and HZWE  
are specied with CL = 5pF as in Fig. 2. Transition is  
measured ±200mV from steady state voltage.  
t
t
t
t
t
t
7. At any given temperature and voltage condition,  
tHZCE is less thantLZCE, and HZWE is less than  
t
tLZWE.  
able  
levels.  
8. WE\ is HIGH for READ cycle.  
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
CE\ > (Vcc -0.2V)  
VIN > (Vcc -0.2V) or < 0.2V  
SYMBOL  
MIN  
MAX  
UNITS NOTES  
VCC for Retention Data  
VDR  
2
V
Data Retention Current  
(L Version Only)  
VCC = 2V  
ICCDR  
4.5  
mA  
Chip Deselect to Data  
Retention Time  
0
ns  
4
t
CDR  
Operation Recovery Time  
10  
ms  
4, 11  
t
R
Micross Components reserves the right to change products or specications without notice.  
AS5C4008  
Rev. 6.4 01/10  
5