FLASH
AS8F128K32
the command register contents are altered.
DEVICE BUS OPERATIONS
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing wave-
NOTE: All device/algorithm descriptions contained in this
data sheet reference each individual die.
This section describes the requirements and use of the
device bus operations, which are initiated through the inter-
nal command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations table lists
the inputs and control levels required, and the resulting output.
The following subsections describe each of these operations in
further detail.
forms. ICC1 in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing sectors of
memory), the system must drive WEx\ and CEx\ to VIL, and
OE\ to VIH.
An erase operation can erase one sector, multiple sectors, or
the entire device. The SectorAddress Tables indicate the address
space that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. See the
“Command Definitions” section for details on erasing a sector
or the entire chip.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CEx\ and OE\ pins to VIL. CEx\ is the power control and
selects the device. OE\ is the output control and gates array
After the system writes the autoselect command se-
quence,
data to the output pins. WEx\ should remain at VIH.
the device enters the autoselect mode. The system can then read
The internal state machine is set for reading array data autoselect codes from the internal register (which is separate
upon device power-up. This ensures that no spurious altera- from the memory array) on I/O31–I/O0. Standard read cycle
tion of the memory content occurs during the power transition. timings apply in this mode. Refer to the “Autoselect Mode”
No command is necessary in this mode to obtain array data. and “Autoselect Command Sequence” sections for more
Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until
information. ICC2 in the DC Characteristics table represents
the active current specification for the write mode. The “AC
Characteristics” section contains timing specification tables
TABLE 1: Device Bus Operations1
ADRESSES
(A16:A0)
OPERATION
CEx\
OE\
WEx\
I/O0 - I/O31
Read
L
L
L
H
X
H
X
X
H
L
A
D
OUT
IN
IN
Write
A
D
IN
Standby
V
0.5V
X
H
X
X
X
High-Z
High-Z
High-Z
CC
Output Disable
L
X
X
X
X
Hardware Reset
Temporary Sector Unprotect
LEGEND:
A
D
IN
IN
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
NOTES:
1. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
Micross Components reserves the right to change products or specifications without notice.
AS8F128K32
Rev. 2.8 01/10
3
MICROSS [ MICROSS COMPONENTS ]
