SRAM
AS8S512K32
& AS8S512K32A
NOTES
1. All voltages referenced to VSSꢀ(GND).
2.ꢀꢀ-2Vꢀforꢀpulseꢀwidthꢀ<20ns.
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE
.
8.ꢀꢀWE\ꢀisꢀHIGHꢀforꢀREADꢀcycle.
3.ꢀꢀICC is dependent on output loading and cycle rates.
9.ꢀꢀDeviceꢀisꢀcontinuouslyꢀselected.ꢀꢀChipꢀselectsꢀandꢀoutputꢀ
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
ꢀꢀꢀꢀꢀTheꢀspecifiedꢀvalueꢀappliesꢀwithꢀtheꢀoutputs
1
HZ.
unloaded, and f=
t
RC(MIN)
11. tRC=ꢀREADꢀcycleꢀtime.
12.ꢀꢀChipꢀenableꢀ(CS\)ꢀandꢀwriteꢀenableꢀ(WE\)ꢀcanꢀinitiateꢀ
andꢀterminateꢀaꢀWRITEꢀcycle.
4.ꢀꢀThisꢀparameterꢀguaranteedꢀbutꢀnotꢀtested.
5.ꢀꢀTestꢀconditionsꢀasꢀspecifiedꢀwithꢀoutputꢀloadingꢀas
shown in Fig. 1 unless otherwise noted.
6. tHZCS, tHZOE and tHZWEꢀareꢀspecifiedꢀwithꢀCL= 5pF as in Fig. 2.
Transitionꢀisꢀmeasuredꢀ+/-ꢀ200ꢀmVꢀtypicalꢀfromꢀsteadyꢀstateꢀ
voltage, allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
13.ꢀꢀICC is for 32 bit mode.
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
V
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
VCC = 2V
CC = 3V
ICCDR
ICCDR
10
12
mA
mA
Data Retention Current
V
CS\ = Vcc + 0.2V
Chip Deselect to Data
Retention Time
0
ns
ns
4
t
CDR
Operation Recovery Time
4, 11
t
t
RC
R
LOW VCC DATA RETENTION WAVEFORM
DATAꢀRETENTIONꢀMODE
VCC
4.5V
4.5V
VDR>2V
tCDR
tR
VDR
CS\ꢀ1-4
Micross Components reserves the right to change products or specifications without notice.
AS8S512K32 & AS8S512K32A
Rev. 6.9 08/13
8
MICROSS [ MICROSS COMPONENTS ]
