SRAM
Austin Semiconductor, Inc.
NOTES
1. All voltages referenced to V
SS
(GND).
2. -3v for pulse width <20ns.
3. I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
1
open, and f=
H
Z.
t
RC(MIN)
4. This parameter is sampled.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. t
HZCE
, t
HZOE
and t
HZWE
are specified with C
L
= 5pF
as in Fig. 2. Transition is measured +/- 200 mV
typical from steady state coltage, allowing for actual
tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE
, is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8.
?
W
/
E is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. t
RC
= READ cycle time.
12. Chip enable (?C
/
E) and write enable (?W
/
E) can initiate and
terminate a WRITE cycle.
13. 32 bit operation
AS8S128K32
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
CE\ > V
CC
- 0.2V
V
IN
> V
CC
- 0.2V
V
CC
= 2.0V
V
CC
= 3V
SYMBOL
V
DR
I
CCDR
I
CCDR
t
CDR
t
R
MIN
2
--
--
0
t
RC
MAX
--
6
11.6
--
UNITS
V
mA
mA
ns
ns
4
4, 11
NOTES
LOW V
CC
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR
>2V
Vcc
tCDR
V
IH
4.5V
4.5V
tR
VDR
CE\
V
IL
AS8S128K32
Rev. 3.5 7/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
MICROSS [ MICROSS COMPONENTS ]
