SRAM
MT5C1001
Limited Availability
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
tWC
tWC
ADDRESS
tA
tA
W
W
tAH
tAH
tAS
tCW
tAS
tCW
CE\
tW
P
tWP1
WE\
tDH
t
tDS
tDH
DS
DATA VAILD
D
Q
HIGH Z
7, 12
WRITE CYCLE NO. 2
(Write Enabled Controlled)
tW
tW
C
C
ADDRESS
tAW
tAW
tAH
tAH
tCW
tCW
CE\
tAS
tAS
t
tWP1
WP
WE\
tDS
tDH
tDH
D
Q
DATA VALID
tHZWE
tLZWE
HIGH-Z
DON’T CARE
UNDEFINED
NOTE: Output enable (OE\) is inactive (HIGH).
Micross Components reserves the right to change products or specifications without notice.
MT5C1001
Rev. 2.2 01/10
7