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5962-8959816MZA 参数 Datasheet PDF下载

5962-8959816MZA图片预览
型号: 5962-8959816MZA
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 45ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32]
分类和应用: 输入元件静态存储器输出元件内存集成电路
文件页数/大小: 17 页 / 212 K
品牌: MICROSS [ MICROSS COMPONENTS ]
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SRAM  
MT5C1008  
AC TEST CONDITIONS  
Input pulse levels ................................... Vss to 3.0V  
Input rise and fall times ....................................... 5ns  
Input timing reference levels ............................. 1.5V  
Output reference levels ..................................... 1.5V  
Output load .............................. See Figures 1 and 2  
480  
Q
Q
30  
5 pF  
255  
Fig. 1 Output Load  
Equivalent  
Fig. 2 Output Load  
Equivalent  
7. At any given temperature and voltage condition,  
NOTES  
t
tHZCE is less thantLZCE, and HZWE is less than  
1. All voltages referenced to VSS (GND).  
2. -2V for pulse width < 20ns  
tLZWE and tHZOE is less than tLZOE.  
8. WE\ is HIGH for READ cycle.  
3. ICC is dependent on output loading and cycle rates.  
The specied value applies with the outputs  
9. Device is continuously selected. Chip enables and  
output enables are held in their active state.  
10. Address valid prior to, or coincident with, latest  
occurring chip enable.  
unloaded, and f =  
1
Hz.  
tRC (MIN)  
4. This parameter is guaranteed but not tested.  
5. Test conditions as specied with the output loading  
as shown in Fig. 1 unless otherwise noted.  
6. tLZCE, LZWE, LZOE, HZCE, HZOE and HZWE  
are specied with CL = 5pF as in Fig. 2. Transition is  
measured ±200mV typical from steady state voltage,  
allowing for actual tester RC time constant.  
t
11. RC = Read Cycle Time.  
12. CE2 timing is the same as CE1\ timing. The  
waveform is inverted.  
13. Chip enable (CE1\, CE2) and write enable (WE\) can  
initiate and terminate a WRITE cycle.  
t
t
t
t
t
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
SYMBOL  
MIN  
MAX  
UNITS NOTES  
2
---  
V
VCC for Retention Data  
VDR  
CE\ > (VCC - 0.2V)  
Data Retention Current  
1.0  
---  
mA  
VCC = 2V  
ICCDR  
V
IN > (VCC - 0.2V)  
or < 0.2V, f=0  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
0
ns  
ns  
4
Operation Recovery Time  
4, 11  
tRC  
LOW Vcc DATA RETENTION WAVEFORM  
DATA RETENTION MODE  
VCC  
4.5V  
4.5V  
VDR > 2V  
tCDR  
tR  
VIH  
CE1\  
VIL  
VDR  
DON’T CARE  
UNDEFINED  
VIH  
VIL  
CE2  
<VSS + 0.2V  
Micross Components reserves the right to change products or specications without notice.  
MT5C1008  
Rev. 6.8 01/10  
5