SRAM
MT5C1009
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
480
Q
Q
30
5 pF
255
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
7. At any given temperature and voltage condition,
NOTES
t
tHZCE is less thantLZCE, and HZWE is less than
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
tLZWE and tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
unloaded, and f =
1
Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, LZWE, LZOE, HZCE, HZOE and HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
t
11. RC = Read Cycle Time.
t
t
t
t
t
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS NOTES
2
---
V
VCC for Retention Data
VDR
CE\ > (VCC - 0.2V)
0.75
1.0
---
mA
mA
ICCDR1
*
VIN > (VCC - 0.2V)
or < 0.2V
Data Retention Current
VCC = 2V
ICCDR2
Chip Deselect to Data
Retention Time
tCDR
tR
0
ns
ns
4
Operation Recovery Time
4, 11
tRC
* Low Power, -20 device only
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tR
tCDR
VIH
CE1\
VIL
VDR
DON’T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
MT5C1009
Rev. 6.2 01/10
5