SRAM
MT5C1009
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A12
DQ8
262,144-BIT
MEMORY ARRAY
DQ1
CE\
COLUMN DECODER
OE\
WE\
A8 A9 A10 A11 A13 A14 A15 A16
POWER
DOWN
NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.
TRUTHTABLE
CE\
WE\
OE\
MODE
I/O PIN
SUPPLY CURRENT
I
I
SBT2, ISBC2
H
X
X
Not Selected
High-Z
SBT2, ISBC2
X
L
L
L
X
H
H
L
X
H
L
Not Selected
Output Disable
Read
High-Z
High-Z
DOUT
DIN
ICC
ICC
ICC
X
Write
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1009
Rev. 5.5 8/01
2