SRAM
MT5C2561
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
Q
Q
VTH
=
VTH =
5pF
Fig. 2 Output Load
Equivalent
Fig. 1 Output Load
Equivalent
7. At any given temperature and voltage condition, tHZCE is
less than tLZCE, and tHZWE is less than tLZWE and tHZOE is
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
less than tLZOE
.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
unloaded, and f =
1
Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state volt-
and
terminate a WRITE cycle.
age,
allowing for actual tester RC time constant.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM
MIN
MAX UNITS NOTES
VCC for Retention Data
2
---
V
VDR
CE\ > (VCC - 0.2V)
µA
Data Retention Current
VCC = 2V ICCDR
900
VIN > (VCC - 0.2V)
or < 0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
0
---
ns
ns
4
Operation Recovery Time
4, 11
tRC
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tCDR
tR
VIH
VIL
VDR
CE\
DON’T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
MT5C2561
Rev. 2.8 01/10
5