SRAM
MT5C6404
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
480
Q
Q
255
5 pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is sampled.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
HZCE
and t
HZWE
are specified with CL = 5pF as in Fig.
2. Transition is measured ±500mV typical from steady state
voltage, allowing for actual tester RC time constant.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
t
11. RC = READ Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
V
CC
= 3V
CONDITIONS
SYM
V
DR
I
CCDR
I
CCDR
t
CDR
t
R
MIN
2
---
---
0
t
RC
MAX
---
300
500
---
---
UNITS
V
μA
μA
ns
ns
4
4, 11
NOTES
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
4.5V
V > 2V
DR
t
R
V
DR
CE\
V
IH
V
IL
DON’T CARE
UNDEFINED
MT5C6404
Rev. 1.2 01/10
Micross Components reserves the right to change products or specifications without notice.
5
MICROSS [ MICROSS COMPONENTS ]
