AS8FLC1M32
A system reset would then also reset the FLASH device,
enabling the system microprocessor to read the boot-up
firmware from the FLASH memory array. The device offers two
power-saving features. When addresses have been stable for a
specified amount of time, the device enters the AUTOMATIC
SLEEP MODE. The system can also place the device into the
STANDBY mode. Power consumption is greatly reduced in
both these modes.
the power transition. No command is necessary in this mode to
obtain array data. Standard microprocessor read cycles that
assert valid data on the device address inputs produce valid
data on the data outputs. The device remains enabled for read
access until the command register contents are altered.
See READING ARRAY DATA for more information. Refer
to AC Read Operations table data for timing specifications
relevant to this operational mode.
FLASH
Device Bus Operations
This section describes the use of the command register for setting
and controlling the bus operations. The command register
itself does not occupy any addressable memory locations.
The register is composed of a series of latches that store the
commands, addresses and data information needed to execute
the indicated command. The contents of the register serve as
the input to the internal state machine. The state machine output
dictates the function of the device. Table 1 lists the device bus
operations, the inputs and control/stimulus levels they require,
and the resulting output. The following subsections describe
each of these operations in further detail.
Writing Commands/Command Sequences
To WRITE a command or command sequence, the system must
drive CSx\, WEx\ to VIL and OE\ to VIH.
An ERASE command operation can erase one sector, multiple
sectors, or the entire array. Table 2 indicates the address
space contained within each sector within the array. A sector
address
consists of the address bits required to uniquely select a
sector.
The “Command Definitions” section has details on erasure
of a single, multiple sectors, the entire array or suspending/
resuming the erase operation.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on each of the Data input/output bits
within each byte of the MCM FLASH array. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents that active
current specification for the WRITE mode. The AC
Characteristics section contains timing specifications for Write
Operations.
WE4\
OE\
Operation
Addresses
Data Bus [DQ0-DQx]
D0-D7 Out
D8-D15 Out
D16-D23 Out
D24-D31 Out
D0-D31 Out
D0-D7 In
D8-D15 In
D16-D23 In
D24-D31 In
D0-D31 In
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CSx\ and OE\ pins to VIL. Chip Select CSx\ is the power and
chip select control of the byte or bytes targeted by the system
(user). Output Enable [OE\] is the output control and gates
array data to the output pins. Write (byte) Enables [WEx\]
should remain at VIH levels.
The internal state machine is set for reading array data upon
device power-up, or after a HARDWARE RESET. This
ensures that no spurious alteration of the memory content
occurs during
Table 1
RESET\
CS1\
L
H
H
H
L
L
H
H
H
L
VCC+/-0.3V
H
H
CS2\
H
L
H
H
L
H
L
H
H
L
VCC+/-0.3V
CS3\
H
H
L
H
L
H
H
L
H
L
VCC+/-0.3V
CS4\
H
H
H
L
L
H
H
H
L
L
VCC+/-0.3V
WE1\
WE2\
WE3\
H
H
H
H
L
READ
A0-Ax In
VCC+/-0.3V
X
L
VID
VID
VID
Legend
L
X
L
L
X
L
X
L
L
X
L
X
L
L
X
L
X
L
L
X
L
H
H
H
L
X
H
X
L
L
X
H
L
H
H
L
X
H
X
L
L
X
H
H
L
H
L
X
H
X
L
L
X
H
H
H
L
L
X
H
X
L
L
X
H
WRITE
A0-Ax In
X
H
X
H
H
X
Standby
Output Disable
Reset
Sector Protect
Sector Un-Protect
Temporary Sector Un-Protect
X
X
X
Sector Address, A6=L,
A1=H, A0=L
Sector Address, A6=H,
A1=H, A0=L
A-In
D-In, D-Out
D-In, D-Out
D-In
L= Logic Low=VIL, H= Logic High=VIH, VID= 12.0+/-0.5V, X= Don't Care, Ain=Address In, Dout=Data Out
Notes (*)
AS8FLC1M32B
Rev. 4.1 10/10
Micross Components reserves the right to change products or specifications without notice.
3
MICROSS [ MICROSS COMPONENTS ]
