FLASH
AS8FLC1M32
before executing the erase operation. During erasure, the
device automatically times the erase pulse widths and verifies
proper cell margin.
BLOCK DIAGRAM
68-Ld. CQFP, Package "QT"
Q
CS1\
CS2\
WE2\
CS3\
CS4\
WE4\
WE1\
WE3\
RESET\
OE\
A0-Ax
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data\ Polling) and
DQ6 (toggle) STATUS BITS. After a program or erase cycle
has been completed, the device is ready to read array data or
accept another command.
1M x 8
1M x 8
1M x 8
1M x 8
The SECTOR ERASE ARCHITECTURE allows memory
sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when
shipped from Micross.
I/O0-7
I/O8-15
I/O16-23
I/O24-31
BLOCK DIAGRAM
P
66-Ld. HIP, Package "H"
Hardware data protection measures include a low VCC
detector that automatically inhibits WRITE operations during
power transitions. The hardware sector protection features
disables both program and erase operation in any combination
of the sectors of memory. This can be achieved in-system or
via specially adapted commercial programming equipment.
CS1\
CS2\ CS3\
CS4\
WE\
RESET\
OE\
A0-Ax
1M x 8
1M x 8
1M x 8
1M x 8
The ERASE SUSPEND feature enables the user to put erase
on hold for any period of time to read data from, or program
data to, any sector which is not selected for erasure. True
BACKGROUND ERASE can thus be achieved.
I/O0-7
I/O8-15
I/O16-23
I/O24-31
The device requires only a single 3.3volt power supply for
both READ and WRITE operations. Internally generated and
regulated voltages are provided for the program and erase
functions.
The HARDWARE RESET\ PIN terminates any operation
in progress and resets the internal state machine to a READ
operation. The RESET\ pin may be tied to the system reset
circuitry.
The device is entirely command set compatible with the
JEDEC SINGLE POWER FASH STANDARD. Com-
mands are written to the command register using standard
microprocessor write timings. Register contents serve as
input to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data required for the programming or erase
function(s). Reading data out of the array is similar to reading
from other electrically programmable devices.
LOGIC DIAGRAM (Byte)
VCC
GND
DQ (byte)
RY/BY\
I/O Buffers
Data Latch
State
Control
RESET\
Erase Voltage
Generator
Command
Register
Device programming occurs by executing the program
command sequence. This initiates the EMBEDDED
PROGRAM algorithm that automatically times the WRITE
PULSE widths and cycle and verifies each cell for proper
cell margins. The UNLOCK BYPASS mode facilitates faster
programming times by requiring only two WRITE cycles to
program data instead of four.
WEx\
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CSx\
OE\
Sector
Switches
Y-Decoder
Y-Gating
VCC Detector
Timer
X-Decoder
Cell Matrix
A0-Ax
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm, an
internal algorithm that automatically pre-programs the array
Micross Components reserves the right to change products or specifications without notice.
AS8FLC1M32B
Rev. 4.1 10/10
2
MICROSS [ MICROSS COMPONENTS ]
