PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
C
URRENT
M
ODE
PWM C
ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
T Y P I C A L A P P L I C AT I O N C I R C U I T S
FIGURE 6.
— SLOPE COMPENSATION
(continued)
V
CC
DC BUS
UCx84xA
5V
8(14)
7(12)
V
O
UVLO
S
R
5V
REF
INTERNAL
BIAS
2.5V
V
REF
GOOD LOGIC
R
T
2N222A
7(11)
R
SLOPE
From V
O
C
T
4(7)
OSCILLATOR
6(10)
Q1
C.S.
COMP
1V
R
PWM
LATCH
5(8)
R
3(5)
5(9)
C
R
S
R
i
2R
2(3)
C
F
R
F
1(1)
ERROR
AMP
R
d
Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either
the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.
FIGURE 7.
—
OPEN LOOP LABORATORY FIXTURE
V
REF
R
T
2N2222
4.7K
100K
1K
ERROR AMP
ADJUST
4.7K
5K
I
SENSE
ADJUST
3
I
SENSE
OUTPUT
6
1
UCx84xA
COMP
V
REF
8
A
V
CC
2
V
FB
V
CC
7
0.1µF
0.1µF
1K
OUTPUT
4
R
T
C
T
GROUND
5
C
T
GROUND
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Copyright © 1995
Rev. 1.2 12/95
7
MICROSEMI [ MICROSEMI CORPORATION ]
