Fusion Family of Mixed Signal FPGAs
Fusion Device Architecture Overview
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 4
Bank 2
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Figure 1 •
Bank 3
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
ARM Cortex-M1 Devices
Pigeon Point Devices
MicroBlade Devices
QN108
QN180
PQ208
3
FG256
FG484
FG676
75/22 (20)
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
119/58 (40)
223/109 (40)
252/126 (40)
U1AFS250
2
AFS090
AFS250
M1AFS250
AFS600
M1AFS600
P1AFS600
1
AFS1500
M1AFS1500
P1AFS1500
1
U1AFS1500
2
U1AFS600
2
Notes:
1. Pigeon Point devices are only offered in FG484 and FG256.
2. MicroBlade devices are only offered in FG256.
3. Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
II
R ev i si o n 4
MICROSEMI [ MICROSEMI CORPORATION ]
