LX1689
I N T E G R A T E D
P R O D U C T S
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (
V
_BATT
)................................................................................................. 30V
Digital Input (
ENABLE
).....................................................................................-0.3V to 7V
Analog Inputs Transient Peak (
I_SNS, OC_SNS, OV_SNS)
..............................-25V to +25V
Analog Inputs (
BRITE_IN, EA_IN
).................................................................. -0.3V to 5.5V
Digital Inputs (DIM_CLK,
DIM_MODE, DIV_248
) ......................................... -0.3V to 5.5V
Digital Output (
A
OUT
, B
OUT
) .................................................................-0.3V to V
DD_P
+0.5V
Analog Outputs (
BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT
) ...-0.3V to V
DD_A_
+0.5V
Operating Temperature Range ..................................................................... -45°C – 100°C
Maximum Junction Temperature ...............................................................................125°C
Note:
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PACKAGE PIN OUT
WWW .
Microsemi
.C
OM
GND
A
OUT
B
OUT
DIM_CLK
DIM_MODE
DIV_248
BRITE_C
BRITE_R
BRITE_IN
ENABLE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD_P
VDD_A
V_BATT
OC_SNS
OV_SNS
I_SNS
BRITE_OUT
EA_OUT
EA_IN
I_R
PW P
ACKAGE
(Top View)
THERMAL DATA
PW
Plastic TSSOP 20-Pin
144°C/W
T
HERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JA
).
The
θ
JA
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
P
IN
N
AME
GND
Ground
Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_P LDO regulator. The input of the LDO is the switched V
_BATT
supply. LDO output is normally 5.3V
and is used only to drive the output buffers at A
OUT
and B
OUT
. The external capacitor will be a 100 to 1000nF
ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be
reduced if the combination of output current and input voltage exceeds power dissipation capability of the die.
A buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_A LDO regulator. The input of the LDO is the switched V
_BATT
supply. LDO output is normally
2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is
6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the
combination of output current and input voltage exceeds power dissipation capability of the die. The external
capacitor will be a 100 to 1000nF ceramic dielectric type.
B buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Voltage Input, 3 to 28V input range. V
_BATT
is switched (see ENABLE) to remove power from chip. Two LDO
regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care
must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to
the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type.
D
ESCRIPTION
V
DD_P
A
OUT
V
DD_A
P
ACKAGE
D
ATA
P
ACKAGE
D
ATA
B
OUT
V
_BATT
Copyright
2000
Rev. 1.0b, 2003-03-31
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
MICROSEMI [ MICROSEMI CORPORATION ]
