VSP 94x2A
DATA SHEET
2.5. Display Processing
The peaking filter clock frequency is CLKB36=36 MHz
(27 MHz). The maximum signal frequency of the pic-
ture stored in the memory is 6.75 MHz. Due to a peak-
ing after postscaler, the frequency range of the peak-
ing filter varies with the expansion factor of the
postscaler.
The display processing part contains an integrated tri-
ple 9-bit DAC and performs digital enhancements and
manipulations of the digital video component signal.
Fig. 2–35 shows the block diagram of the display pro-
cessing part.
Peaking filter characteristic
15
2.5.1. Peaking
The luminance peaking filter improves the overall fre-
quency response of the luminance channel. It consists
of two filters working in parallel. They have high pass
(HP) and band pass (BP) characteristics. Their gain
factors are programmable separately (BCOF, HCOF).
Values greater than 4 peak the signal, whereas values
less than 4 attenuate the signal. The high pass and the
band pass filters are equipped with a common coring
algorithm. It is optimized to achieve a smooth display
of grey scales, not to improve the signal-to-noise ratio.
Therefore no artifacts are produced. Coring can be
switched off (YCOR). The Fig. 2–34 shows the block
diagram of the peaking block.
BCOF
HCOF
10
5
0
5
0
0.1
0.2
0.3
0.4
0.5
normalized Frequency (B)
Fig. 2–33: Peaking Filter: Bandpass and Highpass
filter
BP
GAINB
GAINH
coring
HP
AP
Peak_in
Peak_out
Fig. 2–34: Block Diagram Peaking
9402/9432 only
YCOR,
HCOF,
BCOF
PKLY,
PKLU,
PKLV,
COARSEDEL
CHROMAMP FINEDEL
Y
Fine
Delay
Peaking
DCTI
Delay
4:4:4
DAC
Yin
Cin
ayout
Coarse
Delay
8:8:8
DAC
U
auout
DAC
avout
V
THRESHC,
ASCENTCTI
8
656out
ITU656
Encoder
656clk
SHIFTUV,
DPOUT656
Fig. 2–35: Block Diagram of Display Processing
24
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
