DATA SHEET
VSP 94x2A
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 54h
D7
D6
FIOFFOFF
[BP-POS]
Fieldoffset for ITU656 NTSC signals
‘0’: disabled
‘1’: enabled
FIELDBINV
[BP-POS]
Backend field inversion
‘0’: no inversion
‘1’: inversion
D5-D3
D2-D0
HSEG2_10-8
[BP-POS]
Belongs to 51h
Belongs to 50h
HSEG1_10-8
[BP-POS]
Subaddress 55h
D7
CHRMSIG656
[BP-POS]
Chrominance format for 656 output
‘0’: (R−Y), (B−Y) output
‘1’: −(R−Y), −(B−Y) output
D6
VDEL_EN
[BP-POS]
Vertical pulse delay backend (test only)
‘0’: no delay
‘1’: delayed
D5-D3
D2-D0
HSEG4_10-8
[BP-POS]
Belongs to 53h
HSEG3_10-8
[BP-POS]
Belongs to 52h
Subaddress 56h
D7
D6
SHIFTUV
[BP-DAC]
Shift UV subsampling at digital output
‘0’: take first UV couple
‘1’: take second UV couple
VSP9432/42 only
DPOUT656
[BP-DAC]
Enable digital 656 Output
‘0’: disable output
‘1’: enable output
Subaddress 57h
D7
CHROMSIGN
Chrominance sign
[BP-DAC]
‘0’: (R−Y), (B−Y) output
‘1’: −(R−Y), −(B−Y) output
D6
CHROMAMP
[BP-DAC]
Chrominance amplification
‘0’: amplification=1
‘1’: amplification=2
Subaddress 58h
D7-D0
PKLY
[BP-DAC]
Voltage Level for Y DAC Output
‘00000000’: 0.4 V
‘10000000’: 1.0 V
‘11111111’: 1.9 V
including peaking overshoots. 0.9 V for white max.
Micronas
Aug. 16, 2004; 6251-552-1DS
73
MICRONAS [ MICRONAS ]
