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VSP9425B 参数 Datasheet PDF下载

VSP9425B图片预览
型号: VSP9425B
PDF下载: 下载PDF文件 查看货源
内容描述: PRIMUS强大的扫描速率转换器包括多标准解码器颜色 [PRIMUS Powerful Scan-Rate Converter including Multistandard Color Decoder]
分类和应用: 解码器转换器
文件页数/大小: 126 页 / 1601 K
品牌: MICRONAS [ MICRONAS ]
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VSP 94x2A  
DATA SHEET  
2.5.3. Coarse and Fine Delay  
PKLY  
Before digital-to-analog conversion an adjustment of  
the phase of the luminance is performed. A coarse  
delay from 8 to +7 in steps of 1 pixel CLKB36  
(~28 ns) is possible (COARSEDEL). FINEDEL shifts  
the luminance one CLKB72 (~14 ns) pixel. This can be  
used to compensate delays, if the external processing  
of Y and UV produces different delays (e.g. external  
lowpass filtering).  
128 LSB upper headroom for peaking  
240 LSB normal  
signal range  
'black'  
16 LSB  
2.5.4. Oversampling and DAC  
128 LSB lower headroom for peaking  
After conversion into 8:8:8 format (CLKB72=72 MHz),  
three 9-bit digital-to-analog converters are used for  
analog YUV output. This twofold-oversampling gener-  
ates 1920 active pixels per line (when using recom-  
mended settings) and simplifies the external postfilter-  
ing. The output voltage is determined by PKLY, PKLU  
and PKLV and can be set in a range of 0.4 V ...1.9 V  
(fullscale).  
0 V  
PKLU  
PLLV  
CHROMAMP=1  
CHROMAMP=0  
'no color'  
8 bits of the luminance D/A converter are used for the  
entire signal. The 9th bit is used for over- and under-  
shoots caused by the peaking to prevent or reduce  
clipping artifacts. As the CTI block seldomly produces  
such overshoots, a full-scale operation can be acti-  
vated by CHROMAMP. The output voltages may be  
calculated by:  
Fig. 2–36: DAC Output Signals  
PKLY  
256  
+ 0.36V signalY  
---------------  
VoltageY = 1.56V ⋅  
2.5.5. Output-Sync Controller  
The output sync controller generates horizontal and  
vertical synchronization signals for the scanrate-con-  
verted output signal.  
160....400  
-----------------------  
signalY =  
512  
The number of pixels per line is 4*PPLOP. The default  
value of 288 results in 1152 pixels/line. With  
CLKB= 36 MHz, the horizontal output frequency is  
31.25 kHz, which is twice the PAL horizontal fre-  
quency. Out of these pixels, 16*APPLOP are displayed  
as active picture area, which are 960 by default. The  
position on the screen depends on the NAPPLOP. It  
marks the picture area not active in horizontal direction  
and moves the active picture in horizontal direction.  
The number of lines per field is 2*LPFOP. This value is  
only used in the vertical freeruning mode. In vertical  
locked mode, the number of lines per field is derived  
from the CVBS signal itself and not adjustable. The  
active and non-active picture areas are marked by  
ALPFOP and NALPFOP, respectively.  
[for unpeaked signals max.]  
0....511  
signalY = -----------------  
512  
[for peaked signals max.]  
PKLU, V  
256  
----------------------  
VoltageU, V = 1.56V ⋅  
+ 0.36V CHROMAMP signalUV  
Both generators have a so called ‘locked-mode’ and  
‘freeruning-mode’. Not all combinations of these  
modes make sense. Table 2–13 on page 27 shows  
ingenious configurations.  
128....384  
512  
signalUV = -----------------------  
26  
Aug. 16, 2004; 6251-552-1DS  
Micronas