ADVANCE INFORMATION
VPX 322xE
Contents, continued
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Section
2.10.
2.10.1.
2.10.2.
2.11.
2.12.
2.13.
2.13.1.
2.13.2.
2.13.3.
2.13.3.1.
2.13.3.2.
2.13.3.3.
2.13.3.4.
2.14.
2.14.1.
2.14.2.
2.15.
2.15.1.
2.15.2.
2.15.3.
2.15.4.
2.15.5.
2.16.
2.16.1.
2.16.2.
2.16.3.
2.17.
2.17.1.
2.17.2.
2.17.2.1.
2.17.2.2.
2.17.2.3.
2.17.2.4.
2.17.2.5.
2.17.2.6.
2.17.3.
2.17.4.
2.17.4.1.
2.17.4.2.
2.17.4.3.
2.17.4.4.
2.17.4.5.
2.17.4.6.
2.17.4.7.
2.18.
Title
Operational Modes
Open Mode
Scan Mode
Windowing the Video Field
Temporal Decimation
Data Slicer
Slicer Features
Data Broadcast Systems
Slicer Functions
Input
Automatic Adaptation
Standard Selection
Output
VBI Data Acquisition
Raw VBI Data
Sliced VBI Data
Control Interface
Overview
I
2
C-Bus Interface
Reset and I
2
C Device Address Selection
Protocol Description
FP Control and Status Registers
Initialization of the VPX
Power-on-Reset
Software Reset
Low Power Mode
JTAG Boundary-Scan, Test Access Port (TAP)
General Description
TAP Architecture
TAP Controller
Instruction Register
Boundary Scan Register
Bypass Register
Device Identification Register
Master Mode Data Register
Exception to IEEE 1149.1
IEEE 1149.1–1990 Spec Adherence
Instruction Register
Public Instructions
Self-Test Operation
Test Data Registers
Boundary-Scan Register
Device Identification Register
Performance
Enable/Disable of Output Signals
Micronas
3
MICRONAS [ MICRONAS ]
