VPX 322xE
ADVANCE INFORMATION
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, andAGC. Thecolordecodersep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YC C samples, adjusts the contrast and brightness,
b
r
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note: The VPX 322xE is register compatible with the
VPX322xD family, but not with VPX 3220A, VPX 3216B,
and VPX 3214C family.
HREF
VREF
FIELD
Sync Processing
Clock Gen.
DCO
Text Slicer
(not VPX 3224E)
A[7:0]
OEQ
Y
Y
CVBS/Y
Luma Filter
ADC
Video Decoder
C C
b
C C
b r
r
Chroma
Demodulator
B[7:0]
ADC
Chroma
PIXCLK
LLC
VACT
Line Store
SDA
SCL
I2C
JTAG
Fig. 1–1: Block diagram of the VPX 322xE
MICRONAS INTERMETALL
7
MICRONAS [ MICRONAS ]
