VPC 323xD, VPC 324xD
ADVANCE INFORMATION
FP Sub-
address
Function
Default
Name
h’61
pll frequency limiter, 8%
12.27 MHz30
54 LLC_DFLIMIT
13.5 MHz 54
14.75 MHz62
16 MHz
18 MHz
48
54
h’6d
llc clock generator control word
bit[5:0] hardware register shadow
llc_clkc = 5→12.27 MHz
llc_clkc = 5→13.5 MHz
llc_clkc = 35→14.75 MHz
llc_clkc = 3→16 MHz
2053 LLC_CLKC
llc_clkc = 3→18 MHz
bit[10:6] reserved
bit[11]
0/1 enable/disable llc pll
46
Micronas