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VPC324XD 参数 Datasheet PDF下载

VPC324XD图片预览
型号: VPC324XD
PDF下载: 下载PDF文件 查看货源
内容描述: 梳状滤波器,视频处理器 [Comb Filter Video Processor]
分类和应用:
文件页数/大小: 78 页 / 1187 K
品牌: MICRONAS [ MICRONAS ]
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ADVANCE INFORMATION  
VPC 323xD, VPC 324xD  
Table 3–3: Control Registers of the Fast Processor that are used for the control of DDP 3300A  
– this function is only available in the 50 Hz version (VPC 324xD)  
– default values are initialized at reset  
– * indicates: register is initialized according to the current standard when SDT register is changed  
FP Sub- Function  
address  
Default  
Name  
FP Display Control Register  
(0...1023)  
White Drive Green (0...1023)  
White Drive Blue (0...1023)  
h’130  
h’131  
h’132  
h’139  
White Drive Red  
700  
700  
700  
WDR 1)  
WDG 1)  
WDB 1)  
IBR  
Internal Brightness, Picture (0 ..511), the center value is 256, the range 256  
allows for both increase and reduction of brightness.  
h’13c  
Internal Brightness, measurement (0...511), the center value is 256,  
the brightness for measurement can be set to measure at higher cutoff  
current. The measurement brightness is independent of the drive val-  
ues.  
256  
IBRM  
h’13a  
h’13b  
Analog Brightness for external RGB (0...511), the center value is 256,  
the range allows for both increase and reduction of brightness.  
256  
350  
ABR  
ACT  
Analog Contrast for external RGB (0...511)  
1) The white drive values will become active only after writing the blue value WDB, latching of new values is indi-  
cated by setting the MSB of WDB.  
FP Display Control Register, BCL  
h’144  
h’142  
h’143  
h’145  
h’105  
BCL threshold current, 0...2047 (max ADC output ~1152)  
BCL time constant 0...15 13 ... 1700 msec  
BCL loop gain. 0..15  
1000  
15  
0
BCLTHR  
BCLTM  
BCLG  
BCL minimum contrast 0 ...1023  
307  
0
BCLMIN  
BCLTST  
Test register for BCL/EHT comp. function, register value:  
0
1
normal operation  
stop ADC offset compensation  
x>1 use x in place of input from Measurement ADC  
FP Display Control Register, Deflection  
h’103  
h’102  
interlace offset, –2048 ...2047  
This value is added to the SAWTOOTH output during one field.  
0
7
INTLC  
DSCC  
discharge sample count for deflection retrace,  
SAWTOOTH DAC output impedance is reduced for DSCC lines after  
vertical retrace.  
h’11f  
vertical discharge value,  
–1365  
DSCV  
SAWTOOTH output value during discharge operation, typically same  
as A0 init value for sawtooth.  
h’10b  
h’10a  
EHT (electronic high tension) compensation coefficient, 0...511  
0
EHT  
EHT time constant. 0 ..15 3.2 ...410 msec  
15  
EHTTM  
Micronas  
47  
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