ADVANCE INFORMATION
VPC 323xD, VPC 324xD
amplitude, the external controller reads this register,
calculates the vertical scaling coefficient and transfers
the new settings, e.g. vertical sawtooth parameters,
horizontal scaling coefficient etc., to the VPC.
dB
20
15
10
5
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are pro-
cessed as non-black lines. Therefore the subtitles are
visible on the screen. To suppress the subtitles, the
vertical zoom coefficient is calculated by selecting the
larger number of black lines only. Dark video scenes
with a low contrast level compared to the letterbox area
are indicated by the BLKPIC bit.
0
-5
-10
2
4
6
8
10
MHz
2.9. Control and Data Output Signals
Fig. 2–13: Peaking characteristics
The VPC 32xx supports two output modes: In
DIGIT3000 mode, the output interfaces run at the main
system clock, in line-locked mode, the VPC generates
an asynchronous line-locked clock that is used for the
output interfaces. The VPC delivers either a YCrCb
4:2:2 or a YCrCb 4:1:1 data stream, each with separate
sync information. In case of YCrCb 4:2:2 format, the
VPC32xxD also provides an interface with embedded
syncs according to ITU-R656.
2.6. Vertical Scaler
For PIP operation, the vertical scaler compresses the
incoming 4:2:2 YCrCb active video signal in vertical
direction. It supports a vertical compression ratio of
1(= no compression), 2, 3, 4 and 6.
In case of a vertical compression of 2, 4 and 6, the fil-
ter performs the PAL compensation automatically and
the standard PAL delay line should be bypassed (see
2.3.8.).
2.9.1. Line-Locked Clock Generation
An on-chip rate multiplier is used to synthesize any
desired output clock frequency of 13.5/16/18 MHz. A
double clock frequency output is available to support
100 Hz systems. The synthesizer is controlled by the
embedded RISC controller, which also controls all
front-end loops (clamp, AGC, PLL1, etc.). This allows
the generation of a line-locked output clock regardless
of the system clock (20.25 MHz) which is used for
comb filter operation and color decoding. The control
of scaling and output clock frequency is kept indepen-
dent to allow aspect ratio conversion combined with
sample rate conversion. The line-locked clock circuity
generates control signals, e.g. horizontal/vertical sync,
active video output, it is also the interface from the
internal (20.25 MHz) clock to the external line-locked
clock system.
2.7. Contrast and Brightness
The VPC32xxD provides a selectable contrast and
brightness adjustment for the luma samples. The con-
trol ranges are:
– 0 ≤contrast ≤63/32
– −128 ≤ brightness ≤ 127
Note: for ITU-R luma output code levels (16 ... 240),
contrast has to be set to 48 and brightness has to be
set to 16!
2.8. Blackline Detector
If a line-locked clock is not required, i.e. in the
DIGIT3000 mode, the system runs at the 20.25 MHz
main clock. The horizontal timing reference in this
mode is provided by the front-sync signal. In this case,
the line-locked clock block and all interfaces run from
the 20.25 MHz main clock. The synchronization sig-
nals from the line-locked clock block are still available,
but for every line the internal counters are reset with
the main-sync signal. A double clock signal is not avail-
able in DIGIT3000 mode.
In case of a letterbox format input video, e.g. Cinema-
scope, PAL+ etc., black areas at the upper and lower
part of the picture are visible. It is suitable to remove or
reduce these areas by a vertical zoom and/or shift
operation.
The VPC 32xx supports this feature by a letterbox
detector. The circuitry detects black video lines by
measuring the signal amplitude during active video.
For every field the number of black lines at the upper
and lower part of the picture are measured, compared
to the previous measurement and the minima are
stored in the I2C-register BLKLIN. To adjust the picture
Micronas
17
MICRONAS [ MICRONAS ]
