VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.12. Characteristics, Clock Output Specification
Line-Locked Clock Pins: LLC1, LLC2
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
CL
Load capacitance
–
–
50
pF
13.5 MHz Line Locked Clock
1/T
LLC1 Clock Frequency
LLC1 Clock Low Time
LLC1 Clock High Time
LLC2 Clock Frequency
LLC2 Clock Low Time
LLC2 Clock High Time
12.5
22
25
25
5
–
–
–
–
–
–
14.5
–
MHz
ns
13
WL13
WH13
t
t
C = 30 pF
L
–
ns
C = 30 pF
L
1/T
29
–
MHz
ns
27
WL27
WH27
t
t
C = 30 pF
L
10
–
ns
C = 30 pF
L
16 MHz Line Locked Clock
14.8
18 MHz Line Locked Clock
16.6
common timings – all modes
1/T
1/T
LLC1 Clock Frequency
LLC1 Clock Frequency
–
17.2
19.4
MHz
MHz
13
13
–
t
Clock Skew
0
–
–
–
–
–
–
–
4
ns
ns
ns
V
SK
t , t
Clock Rise/Fall TimeClock
Clock Rise/Fall TimeClock
Input Low Voltage
–
5
LLC1=13.5MHz, C = 30 pF
L
R
F
t , t
–
10
0.8
–
LLC2=27.0MHz, C = 30 pF
L
R
F
V
V
V
V
–
IL
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
–
V
IH
OL
0.4
–
V
I
I
= 2 mA
L
2.4
V
= –2 mA
OH
H
T
13
t
t
WL13
WH13
VIH
VIL
LLC1
(13.5 MHz ±7%)
t
F
t
R
t
t
SK
SK
t
t
T
WL27
WH27
27
VIH
VIL
LLC2
(27 MHz ±7%)
t
t
F
R
Fig. 4–18: Line-locked clock output pins
70
Micronas
MICRONAS [ MICRONAS ]
