VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.7. Characteristics, Analog Video and Component Inputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
Analog Input Voltage
VIN1, VIN2
VIN3, VIN4
CIN
0
–
3.5
V
VIN
R1/CR1IN
G1/Y1IN
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
C
C
C
Input Coupling Capacitor
Video Inputs
VIN1, VIN2
VIN3, VIN4
–
–
–
680
1
–
–
–
nF
nF
nF
CP
CP
CP
Input Coupling Capacitor
Chroma Input
CIN
Input Coupling Capacitor
Component Input
R1/CR1IN
G1/Y1IN
220
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
4.6.4.8. Characteristics, Analog Front-End and ADCs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
Reference Voltage Top
VRT
2.4
2.5
2.6
V
10 µF/10 nF, 1 GΩ Probe
VRT
VREF
Luma – Path
R
Input Resistance
Input Capacitance
VIN1
VIN2
VIN3
VIN4
1
MΩ
Code Clamp–DAC=0
VIN
C
4.5
pF
VIN
V
V
Full Scale Input Voltage
Full Scale Input Voltage
AGC step width
VIN1
VIN2
VIN3
VIN4
1.8
0.5
2.0
2.2
0.7
V
V
min. AGC Gain
VIN
VIN
PP
0.6
max. AGC Gain
PP
AGC
DNL
0.166
dB
LSB
V
6-Bit Resolution= 64 Steps
f
=1MHz,
sig
– 2 dBr of max. AGC–Gain
AGC Differential Non-Linearity
Input Clamping Level, CVBS
±0.5
AGC
VINCL
V
VIN1
VIN2
VIN3
VIN4
1.0
Binary Level = 64 LSB
min. AGC Gain
Q
Clamping DAC Resolution
–16
15
steps
µA
5 Bit – I–DAC, bipolar
CL
V
=1.5 V
VIN
I
Input Clamping Current per step
0.7
1.0
1.3
±0.5
CL–LSB
DNL
Clamping DAC Differential Non-
Linearity
LSB
ICL
64
Micronas
MICRONAS [ MICRONAS ]
