VPC 323xD, VPC 324xD
ADVANCE INFORMATION
3. Serial Interface
The registers of the VPC have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
3.1. I2C-Bus Interface
Communication between the VPC and the external
controller is done via I2C-bus. The VPC has an I2C-bus
slave interface and uses I2C clock synchronization to
slow down the interface if required. The I2C-bus inter-
face uses one level of subaddress: one I2C-bus
address is used to address the IC and a subaddress
selects one of the internal registers. For multi
VPC32xxD applications the following three I2C-bus
chip addresses are selectable via I2CSEL pin:
Figure 3–1 shows I2C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
3.2. Control and Status Registers
Table 3–1 gives definitions of the VPC control and sta-
tus registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read opera-
tions. Write registers that can be read back are indi-
cated in Table 3–1.
A6 A5 A4 A3 A2 A1 A0 R/W I2CSEL
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1/0 VSUP
1/0 VRT
1/0 GND
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 3–1.
I2C write access
send FP-address-
send FP-address-
S
S
1000 111 W Ack
1000 111 W Ack
FPWR
Ack
Ack
P
P
Ack
Ack
Ack
Ack
byte high
byte low
to FP
send data-
byte high
send data-
byte low
FPDAT
I2C read access
to FP
send FP-address-
byte high
send FP-address-
byte low
S
S
1000 111 W Ack
1000 111 W Ack
FPRD
Ack
Ack
P
Ack
R
Ack
receive data-
byte high
FPDAT
S
1000 111
Ack
Ack
Nak
receive data-
byte low
P
I2C write access
subaddress 7c
S
S
1000 111 W Ack
1000 111 W Ack
0111 1100
0111 1100
Ack 1 or 2 byte Data
P
I2C read access
subaddress 7c
Ack
S
1000 111
R Ack high byte Data
Ack
low byte Data Nak P
W
R
Ack
Nak
S
=
=
=
=
=
=
0
1
0
1
Start
Stop
1
0
SDA
SCL
S
P
P
Fig. 3–1: I2C-bus protocols
30
Micronas
MICRONAS [ MICRONAS ]
