VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.11. Video Sync Processing
For vertical sync separation, the sliced video signal is
integrated. The FP uses the integrator value to derive
vertical sync and field information.
Fig. 2–18 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is
separated by a slicer; the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator mea-
sures the falling edge of sync, as well as the integrated
sync pulse.
The information extracted by the video sync process-
ing is multiplexed onto the hardware front sync signal
(FSY) and is distributed to the rest of the video pro-
cessing system. The format of the front sync signal is
given in Fig. 2–19.
The data for the vertical deflection, the sawtooth, and
the East-West correction signal is calculated by the
VPC 32xx. The data is buffered in a FIFO and trans-
ferred to the back-end IC DDP 3300A by a single wire
interface.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it
thus counts synchronously to the video signal.
Frequency and phase characteristics of the analog
video signal are derived from PLL1. The results are fed
to the scaler unit for data interpolation and orthogonal-
ization and to the clock synthesizer for line-locked
clock generation. Horizontal and vertical syncs are
latched with the line-locked clock.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/mini-
mum of the video signal. This information is processed
by the FP and used for gain control and clamping.
PLL1
lowpass
1 MHz
&
phase
comparator
&
front sync
front
horizontal
sync
separation
skew
sync
counter
generator
vblank
field
syncslicer
lowpass
video
input
clock
synthesizer
syncs
frontend
timing
clock
H/V syncs
clamp &
signal
meas.
clamping, colorkey, FIFO_write
Sawtooth
vertical
vertical
sync
separation
vertical
serial
data
Parabola
FIFO
E/W
sawtooth
Calculation
Fig. 2–18: Sync separation block diagram
skew
LSB
skew not
used
V: vertical sync
0 = off
F1
F
V
MSB
input
analog
Parity
1 = on
F0 reserved
video
F: field #
(not in scale)
0 = field 1
1 = field 2
FSY
F0
F1
Fig. 2–19: Front sync format
22
Micronas
MICRONAS [ MICRONAS ]
