PRELIMINARY DATA SHEET
VDP 31xxB
2
I C sub
Number
Mode
Function
Default
Name
address of bits
digital OSD insertion contrast for R (amplitude range: 0 to 255)
h’4c
h’48
h’44
9
9
9
w v
bit [3:0]
0..13
14,15
R amplitude = CLUTn · (DRCT + 4)
invalid
8
8
DRCT
picture frame insertion contrast for R (ampl. range: 0 to 255)
bit [7:4]
0..13
14,15
R amplitude = PFCR · (PFRCT + 4)
invalid
PFRCT
digital OSD insertion contrast for G (amplitude range: 0 to 255)
w v
w v
bit [3:0]
0..13
14,15
G amplitude = CLUTn · (DGCT + 4)
invalid
8
8
DGCT
picture frame insertion contrast for G (ampl. range: 0 to 255)
bit [7:4]
0..13
14,15
G amplitude = PFCG · (PFGCT + 4)
invalid
PFGCT
digital OSD insertion contrast for B (amplitude range: 0 to 255)
bit [3:0]
0..13
14,15
B amplitude = CLUTn · (DBCT + 4)
invalid
8
8
DBCT
picture frame insertion contrast for B (ampl. range: 0 to 255)
bit [7:4]
0..13
B amplitude = PFCB · (PFBCT + 4)
PFBCT
14,15
invalid
PICTURE FRAME GENERATOR
h’4F
9
w v
bit [8:0] horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
0
PFGHB
h’53
h’63
9
9
w v
w v
bit [8:0] horizontal picture frame end
0
PFGHE
PFGVB
bit [8:0] vertical picture frame begin
code 0 = picture frame generator vertically disabled
270
h’6f
9
w v
bit [8:0] vertical picture frame end
56
PFGVE
enable and priority – see under ‘PRIORITY BUS’
picture frame color – see under ‘COLOR LOOK-UP TABLE’
SCAN VELOCITY MODULATION
h’62
h’5e
h’5a
h’56
9
9
9
9
w v
w v
w v
w v
video mode coefficients
bit [5:0]
bit [8:6]
gain1
60
4
SVG1
SVD1
differentiator delay 1 (0= filter off, 1...6= delay)
text mode coefficients
bit [5:0]
bit [8:6]
gain 2
60
4
SVG2
SVD2
differentiator delay 2 (0= filter off, 1...6= delay)
limiter
bit [6:0]
bit [8:5]
limit value
not used, set to ”0”
100
0
SVLIM
delay and coring
bit [3:0]
adjustable delay, in 1/2 display clock steps,
(value 5 : delay of SVMOUT is the same as for
7
0
SVDEL
SVCOR
RGBOUT
coring value
not used, set to ”0”
bit [7:4]
bit [8]
Micronas
35
MICRONAS [ MICRONAS ]
