ADVANCE INFORMATION
VDP 313xY
2.14.Serial Interface
Table 2–3: I2C Chip Addresses
2.14.1.I2C-Bus Interface
Chip
A6 A5 A4 A3 A2 A1 A0 R/W
Address
Communication between the VDP and the external
controller is done via I2C-bus. The VDP has two
I2C-bus slave interfaces (for compatibility with VPC/
DDP applications) - one in the front-end and one in the
back-end. Both I2C-bus interfaces use I2C clock syn-
chronization to slow down the interface if required.
Both I2C-bus interfaces use one level of subaddress:
the I2C-bus chip address is used to address the IC and
a subaddress selects one of the internal registers. The
I2C-bus chip addresses are given below:
front-end
back-end
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1/0
1/0
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Fig. 2–27 shows I2C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
I2C write access
send FP-address-
byte high
send FP-address-
S
S
1000 111 W Ack
1000 111 W Ack
FPWR
FPDAT
Ack
Ack
Ack
Ack
Ack P
Ack P
byte low
to FP
send data-
byte high
send data-
byte low
I2C read access
to FP
send FP-address-
byte high
send FP-address-
byte low
S
S
1000 111 W Ack
1000 111 W Ack
FPRD
Ack
Ack
Ack P
receive data-
byte high
FPDAT
Ack S 1000 111 R Ack
Ack
receive data-
byte low
Nak
P
I2C write access
subaddress 7c
S
S
1000 111 W Ack 0111 1100 Ack 1 or 2 byte Data
P
I2C read access
subaddress 7c
1000 111 W Ack 0111 1100 Ack S 1000 111 R Ack high byte Data Ack
low byte Data Nak P
W
R
Ack
Nak
S
=
=
=
=
=
=
0
1
0
1
Start
Stop
1
0
SDA
SCL
S
P
P
Fig. 2–27: I2C-bus protocols
Micronas
29
MICRONAS [ MICRONAS ]
