ADVANCE INFORMATION
VDP 313xY
2. Functional Description
2.1. Introduction
rent sources. The clamping level is the back porch of
the video signal.
S-VHS chrominance is also AC coupled. The input pin
is internally biased to the center of the ADC input
range.
The VDP 313xY includes complete video, display and
deflection processing. All processing is done digitally,
the video frontend and video backend are interfacing
to the analog world. Most functions of the VDP can be
controlled by software via I2C-Bus interface (see
Section 2.14.1. on page 29).
The chrominance inputs for YCRCB need to be AC
coupled using clamping capacitors. It is strongly rec-
ommended to use 5 MHz anti-alias low-pass filters on
each input. Each channel is sampled at 10.125 MHz
with a resolution of 8 bit and a clamping level of 128.
2.2. Video Front End
This block provides the analog interfaces to all video
inputs and mainly carries out analog-to-digital conver-
sion for the following digital video processing. A block
diagram is given in Fig. 2–1.
2.2.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
The gain of the video input stage including the ADC is
213 steps/V with the AGC set to 0 dB.
Most of the functional blocks in the front-end are digi-
tally controlled (clamping, AGC, and clock-DCO). The
control loops are closed by the Fast Processor (FP)
embedded in the video decoder.
The gain of the chrominance path in the YCRCB mode
is fix and adapted to a nominal amplitude of 0.7 Vpp.
However, if an overflow of the ADC occurs an
extended signal range of 1 Vpp can be selected.
2.2.1. Input Selection
Up to seven analog inputs can be connected. Four
inputs are for input of composite video or S-VHS lumi-
nance signal. These inputs are clamped to the sync
back porch and are amplified by a variable gain ampli-
fier. Two inputs are for connection of S-VHS car-
rier-chrominance signal. These inputs are internally
biased and have a fixed gain amplifier. For analog
YCRCB signals (e.g. from DVD players) the selected
luminance input is used together with CBIN and CRIN.
2.2.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit res-
olution. An integrated bandgap circuit generates the
required reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
2.2.5. Digitally Controlled Clock Oscillator
2.2.2. Clamping
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor. The clock frequency can be
adjusted within ±150 ppm.
The composite video input signals are AC coupled to
the IC. The clamping voltage is stored on the coupling
capacitors and is generated by digitally controlled cur-
AGC
+6/–4.5 dB
VIN1
CVBS/Y
CVBS/Y
CVBS/Y
CVBS/Y
Chroma
Chroma
digital CVBS or Luma
ADC
clamp
bias
VIN2
VIN3
VIN4
CIN1
gain
digital Chroma
ADC
CIN2
CRIN
system clocks
DVCO
±150
ppm
reference
generation
frequency
clamp
CBIN
Chroma
20.25 MHz
Fig. 2–1: Video front-end
Micronas
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MICRONAS [ MICRONAS ]
