欢迎访问ic37.com |
会员登录 免费注册
发布采购

VDP3132Y 参数 Datasheet PDF下载

VDP3132Y图片预览
型号: VDP3132Y
PDF下载: 下载PDF文件 查看货源
内容描述: 视频处理器家族 [Video Processor Family]
分类和应用:
文件页数/大小: 76 页 / 1707 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号VDP3132Y的Datasheet PDF文件第45页浏览型号VDP3132Y的Datasheet PDF文件第46页浏览型号VDP3132Y的Datasheet PDF文件第47页浏览型号VDP3132Y的Datasheet PDF文件第48页浏览型号VDP3132Y的Datasheet PDF文件第50页浏览型号VDP3132Y的Datasheet PDF文件第51页浏览型号VDP3132Y的Datasheet PDF文件第52页浏览型号VDP3132Y的Datasheet PDF文件第53页  
ADVANCE INFORMATION  
VDP 313xY  
Table 28: Control Registers of the Fast Processor for control of the video backend functionsdefault values are  
initializied at reset  
FP Sub-  
address  
Function  
Default  
(hex)  
Name  
(hex)  
FP Display Control Register  
130  
131  
132  
139  
White Drive Red (0...1023)  
700  
700  
700  
WDR 1)  
WDG 1)  
WDB 1)  
IBR  
White Drive Green (0...1023)  
White Drive Blue (0...1023)  
Internal Brightness, Picture (0...511), the center value is 256, the 256  
range allows for both increase and reduction of brightness.  
13C  
Internal Brightness, Measurement (0...511), the center value is  
256, the brightness for measurement can be set to measure at  
higher cutoff current. The measurement brightness is indepen-  
dent of the drive values.  
256  
IBRM  
13A  
13B  
Analog Brightness for external RGB (0...511), the center value is 256  
256, the range allows for both increase and reduction of bright-  
ness.  
ABR  
ACT  
Analog Contrast for external RGB (0...511)  
350  
1) The white drive values will become active only after writing the blue value WDB, latching of new values is indi-  
cated by setting the MSB of WDB.  
FP Display Control Register, BCL  
144  
142  
143  
145  
105  
BCL threshold current, 0...2047 (max ADC output ~1152)  
BCL time constant 0...15 13 ... 1700 ms  
BCL loop gain. 0..15  
1000  
15  
BCLTHR  
BCLTM  
BCLG  
0
BCL minimum contrast 0...1023  
307  
0
BCLMIN  
BCLTST  
Test register for BCL/EHT comp. function, register value:  
0
1
normal operation  
stop ADC offset compensation  
x>1 use x in place of input from Measurement  
ADC  
60  
Current BCL reduction (0...1023; read only)  
1023  
BCLREDUC  
FP Display Control Register, Deflection  
103  
interlace offset, 2048..2047  
This value is added to the SAWTOOTH output during one field.  
0
7
INTLC  
DSCC  
102  
discharge sample count for deflection retrace,  
SAWTOOTH DAC output impedance is reduced for DSCC lines  
after vertical retrace.  
11F  
10B  
vertical discharge value,  
SAWTOOTH output value during discharge operation, typically  
same as A0 init value for sawtooth.  
1365  
DSCV  
EHTV  
EHT compensation vertical gain coefficient, 0...511  
0
Micronas  
49