PRELIMINARY DATA SHEET
VDP 31xxB
2. Functional Description
2.1. Analog Front-End
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC. The
gain of the video input stage including the ADC is 213
steps/V with the AGC set to 0 dB.
This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in Fig. 2–1.
2.1.4. Analog-to-Digital Converters
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The con-
trol loops are closed by the Fast Processor (‘FP’) em-
bedded in the decoder.
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit reso-
lution. An integrated bandgap circuit generates the re-
quired reference voltages for the converters.
2.1.1. Input Selector
2.1.5. ADC Range
Up to five analog inputs can be connected. Four inputs
are for input of composite video or S-VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S-VHS carrier-chrominance signal.
This input is internally biased and has a fixed gain ampli-
fier.
The ADC input range for the various input signals and
the digital representation is given in Table 2–1 and Fig.
2–2. The corresponding output signal levels of the
VDP 31xxB are also shown.
2.1.6. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within ±150 ppm.
2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.
2.1.7. Analog Video Output
The input signal of the Luma ADC is available at the ana-
log video output pin. The signal at this pin must be buff-
ered by a source follower. The output voltage is 2 V, thus
the signal can be used to drive a 75 W line. The magni-
tude is adjusted with an AGC in 8 steps together with the
main AGC.
Analog Video
Output
AGC
+6/–4.5 dB
3
VIN4
VIN3
VIN2
CVBS/Y
CVBS/Y
clamp
bias
ADC
ADC
digital CVBS or Luma
gain
CVBS/Y
VIN1
CIN
CVBS/Y/C
digital Chroma
system clocks
Chroma
DVCO
±150
ppm
reference
frequency
generation
20.25 MHz
Fig. 2–1: Analog front-end
Micronas
7
MICRONAS [ MICRONAS ]
