VDP 31xxB
PRELIMINARY DATA SHEET
2
I C sub
Number
Mode
Function
Default
Name
address of bits
OUTPUT PINS
w/r
h’10
8
output pin configuration
0
bit [2:0]
pin driver strength, MSY and CSY
PSTSY
7 = tristate
6 = minimum strength
0 = maximum strength
reserved (set to 0)
bit [4:3]
bit [5]
VEWXR
CSYM
0/1
disable/enable internal resistor for
vertical and East/West drive output
function of CSY pin :
bit [7:6]
00
01
10
11
composite sync signal output
25 Hz output (field1/field2 signal)
no interlace (field 2), output = 0
1 MHz horizontal drive clock
MISCELLANEOUS
8 w/r fast blank interface mode
h’32
0
FBMOD
FBFOH1
bit [0]
0
1
internal fast blank 1 from FBLIN1 pin
force internal fast blank 1 signal to high
internal fast blank active high/low
disable/enable clamping reference for
RGB outputs
FBPOL
CLMPR
bit [1]
bit [2]
0/1
0/1
FLMW
bit [3]
1
full line MADC measurement window,
disables bit [3] in address h’25
horizontal flyback input active high/low
reserved (set to 0)
internal fast blank 1 from FBLIN1 pin
force internal fast blank 1 signal to low
FLPOL
FBFOL1
bit [4]
bit [6:5]
bit [7]
0/1
0
1
h’31
8
w/r
fast blank interface mode 2
0
FBMOD2
FBFOH2
bit [0]
bit [1]
bit [2]
0
1
0
1
internal fast blank 2 from FBLIN2 pin
force internal fast blank 2 signal to high
internal fast blank 2 from FBLIN2 pin
force internal fast blank 2 signal to low
fast blank input priority
FBFOL2
FBPRIO
0
1
FBLIN1 > FBLIN2
FBLIN1 < FBLIN2
FBMON
HCSEN
bit [3]
bit [4]
bit [5]
fast blank monitor input select
monitor connected to FBLIN1 pin
monitor connected to FBLIN2 pin
half contrast switch enable
PORT0 enable / HCS disable
PORT0 disable / HCS enable
half contrast from HCS pin
force half contrast signal to high
half contrast active high/low at HCS pin
reserved (set to 0)
0
1
0
1
0
1
HCSFOH
HCSPOL
bit [6]
bit [7]
0/1
h’34
16
w/r
IO Port
bit [6:0]
bit [7]
0
IOPORT
IODATA
FSYOEN
data to/from PORT[6:0]
front sync output at PORT1
PORT1 input/output enable
FSY output enable
0
1
IODIR
IOEN
bit [14:8]
bit [15]
port direction
0
1
switch PORT[bit–8] to input
switch PORT[bit–8] to output
port enable
0
1
COLOR[4:0] enable / PORT[6:2] disable
COLOR[4:0] disable / PORT[6:2] enable
38
Micronas
MICRONAS [ MICRONAS ]
