VDP 31xxB
PRELIMINARY DATA SHEET
2.7. Video Sync Processing
For vertical sync separation, the sliced video signal is in-
tegrated. The FP uses the integrator value to derive ver-
tical sync and field information.
Fig. 2–11 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is sep-
arated by a slicer; the sync phase is measured. A vari-
ablewindowcanbeselectedtoimprovethenoiseimmu-
nity of the slicer. The phase comparator measures the
falling edge of sync, as well as the integrated sync pulse.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and is distributed to the rest of the video processing sys-
tem. The format of the front sync signal is given in
Fig. 2–12.
Thedatafortheverticaldeflection, thesawtooth, andthe
East-West correction signal is calculated by the
VDP 31xxB. The data is buffered in a FIFO and trans-
ferred to the back-end by a single wire interface.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
Frequency and phase characteristics of the analog vid-
eo signal are derived from PLL1. The results are fed to
the scaler unit for data interpolation and orthogonaliza-
tion and to the clock synthesizer for line-locked clock
generation. Horizontal and vertical syncs are latched
with the line-locked clock.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
PLL1
lowpass
1 MHz
&
phase
comparator
&
front sync
front
horizontal
sync
separation
skew
sync
counter
generator
vblank
field
syncslicer
lowpass
video
input
clock
synthesizer
syncs
front-end
timing
clock
H/V syncs
clamp &
signal
meas.
clamping, colorkey, FIFO_write
Sawtooth
vertical
vertical
sync
separation
vertical
serial
data
Parabola
FIFO
E/W
sawtooth
Calculation
Fig. 2–11: Sync separation block diagram
skew
LSB
skew not
used
V: vertical sync
0 = off
F1
F
V
MSB
input
analog
Parity
1 = on
F0 reserved
video
F: field #
(not in scale)
0 = field 1
1 = field 2
FSY
F0
F1
Fig. 2–12: Front sync format
14
Micronas
MICRONAS [ MICRONAS ]
