PRELIMINARY DATA SHEET
VDP 31xxB
Pin 41, 42, 43, 45, 46, 47 – Analog RGB Inputs, RIN1/2,
GIN1/2, BIN1/2 (Fig. 4–15)
Pin 59 – Analog Video Output, VOUT (Fig. 4–6)
The analog video signal that is selected for the main
(luma, cvbs) adc is output at this pin. An emitter follower
is required at this pin.
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the fast blank
signal. The analog backend provides separate bright-
ness and contrast settings for the external analog RGB
signals.
Pin 60 – Analog Chroma Input, CIN (Fig. 4–9)
This pin is connected to the S-VHS chroma signal. A re-
sistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connected to the chroma (Video 2) A/D converter. The
signal must be AC-coupled.
Pin 44, 48 – Fast Blank Inputs, FBLIN1/2 (Fig. 4–15)
ThesepinsareusedtoswitchtheRGBoutputstotheex-
ternal analog RGB inputs.
Pin61...64–AnalogVideoInput1–4, VIN1–4(Fig. 4–11)
These are the analog video inputs. A CVBS or S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The input signal must be AC-coupled.
Pin 49 – Main Clock Output, CLK20 (Fig. 4–4)
This is the 20.25MHz main system clock, that is used by
all circuits in a high-end VDP system. All external timing
is derived from this clock.
Pin 50 – Horizontal Drive Output, HOUT (Fig. 4–18)
This open drain output supplies the the drive pulse for
the horizontal output stage. The polarity and gating with
the flyback pulse are selectable by software.
4.4. Pin Configuration
1
TEST
RESQ
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VIN4
2
VIN3
3
SCL
VIN2
Pin 51, 52 – Crystal Input and Output, XTAL1, XTAL2
(Fig. 4–7)
SDA
4
VIN1
5
DSGND
PORT0/HCS
PORT1/FSY
CSY
CIN
These pins are connected to an 20.25 MHz crystal oscil-
lator is digitally tuned by integrated shunt capacitances.
The Clk20 and Clk5 clock signals are derived from this
oscillator. An external clock can be fed into XTAL1. In
this case clock frequency adjustment must be switched
off.
6
VOUT
VSUPF
VRT
7
8
MSY
ISGND
GNDF
CLK5
VSTBY
9
INTLC
10
11
12
13
14
15
16
VPROT
SAFETY
HFLB
XTAL2
XTAL1
Pin 53 – Standby Supply Voltage, VSTBY
In standby mode, only the clock oscillator and the hori-
zontal drive circuitry are active.
GNDDF
HOUT
CLK20
VSUPD
GNDDO
48
47
46
45
PR0
17
18
19
20
FBLIN2
BIN2
GIN2
RIN2
FBLIN
BIN
Pin 54 – CCU 5 MHz Clock Output, CLK5 (Fig. 4–10)
This pin provides a clock frequency for the TV microcon-
troller, e.g. a CCU3000 controller.
PR1
PR2
COLOR4/PORT2
COLOR3/PORT3
44
43
42
41
40
39
38
37
36
35
34
33
21
22
23
24
25
26
27
28
29
30
31
32
COLOR2/PORT4
COLOR1/PORT5
COLOR0/PORT6
Pin 55 – Ground (Analog Front-end), GND
F
GIN
RIN
Pin56–Ground(AnalogSignalInput), ISGND(Fig. 4–8)
This is the high quality ground reference for the video
input signals.
VRD
DSGND
RSW2
RSW1
SENSE
GNDM
GNDV
VERT
BOUT
GOUT
ROUT
VSUPO
GNDO
SVMOUT
XREF
Pin 57 – Reference Voltage Top, VRT (Fig. 4–8)
Via this pin, the reference voltage for the A/D converters
is decoupled. The pin is connected with 10 mF/47 nF to
the Signal Ground Pin.
EW
Fig. 4–2: 64-pin PSDIP package
Pin 58 – Supply Voltage (Analog Front-end), VSUP
F
Micronas
51
MICRONAS [ MICRONAS ]
