ADVANCE INFORMATION
VCT 38xxA
Table 5–26: I/O Register Map
Addr.
Mnemonic Name
Mode Reset Section
1F01
CR
Control Register
r/w
−
Control Register (chap-
ter 5.4. on page 87)
1F0F
BR
Banking Register
r/w
01
Memory Banking (chap-
ter 5.8. on page 95)
1F00
1F60
1F07
1F08
1F09
1F0A
1FD0
1FD1
1FD2
1FD3
1FD4
1FD5
1FD6
1FD7
1FDB
1E73
CSW0
CSW1
RC
Clock, Supply & Watchdog Register 0
Clock, Supply & Watchdog Register 1
Reset Control Register
w
r/w
r/w
r/w
r/w
r/w
w
01
FF
00
00
40
00
00
00
00
00
00
00
00
00
02
00
Reset Logic (chapter
5.7. on page 90)
SR0
Standby Register 0
Standby Registers
(chapter 5.5. on
page 89)
SR1
Standby Register 1
SR2
Standby Register 2
I2CWS0
I2CWS1
I2CWD0
I2CWD1
I2CWP0
I2CWP1
I2CRD
I2CRS
I2CM
I2C Write Start Register 0
I2C Write Start Register 1
I2C Write Data Register 0
I2C Write Data Register 1
I2C Write Stop Register 0
I2C Write Stop Register 1
I2C Read Data Register
I2C Read Status Register
I2C Mode Register
I2C-Bus Master Inter-
face (chapter 5.12. on
page 109)
w
w
w
w
w
r
r
w
I2CPS
I2C Port Select Register
w
Micronas
133
MICRONAS [ MICRONAS ]
