VCT 38xxA
ADVANCE INFORMATION
Table 2–5: Control registers of the Fast Processor for control of the video front-end functions
− default values are initializied at reset
FP Sub-
address
Function
Default
Name
Standard Selection
h’20
Standard select:
0
SDT
bit[2:0]
standard
0
1
2
3
4
5
6
7
PAL B,G,H,I (50 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
PAL
NTSC
SECAM
NTSC44
PALM
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
PALN
PAL60
NTSCC
SDTMOD
NTSC COMB (60 Hz)
bit[3]
0/1 standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
bit[4]
bit[5]
bit[6]
reserved (set to 0)
0/1 2-H comb filter off/on
0/1 S-VHS mode off/on (2-H comb is switched off)
COMB
SVHS
Option bits allow to suppress parts of the initialization, this can be used
for color standard search:
SDTOPT
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
2-H comb filter set-up only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
h’148
Enable automatic standard recognition (ASR)
0
ASR_ENA
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
0/1 PAL B,G,H,I
0/1 NTSC M
0/1 SECAM
0/1 NTSC44
0/1 PAL M
(50 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
0/1 PAL N
0/1 PAL 60
bit[10:7] reserved set to 0
bit[11]
1
reset status information ‘switch’ in asr_status
(cleared automatically)
0: disable recognition; 1: enable recognition
Note: For correct operation don’t change FP reg. 20h and 21h, while
ASR is enabled!
40
Micronas
MICRONAS [ MICRONAS ]
